Assignment of Assignor's Interest

Recorded: 1995-10-03 Pages: 3

Assignor

NAKAMURA, YOSHIYUKI

Executed: 1995-09-22

Assignee

NEC CORPORATION

7-1, SHIBA 5-CHOME, MINATO-KU, TOKYO, JAPAN

Covered Property (1)

Integrated Logic Circuit with Partial Scan Path Circuit and Partial Scan Path Design Method for Same

Patent: 5,627,841 →

Application: 08/538,228 →

Related Assignments (1)

Other recorded transfers of the patent in this record — the chain of ownership.