IP Library › Assignment 009300/0309

Patent Assignment

Reel/Frame 009300/0309

Change of State of Incorporation

Recorded: 1998-07-06 Pages: 18

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Assignor

ADAPTEC, INC.

Executed: 1997-11-19

Assignee

ADAPTEC, INC.

691 S. MILPITAS BLVD., MILPITAS, CALIFORNIA, 95035

Covered Properties (47)

Intelligent Hardware for Automatically Reading and Writing Multiple Sectors of Data Between a Computer Bus and a Disk Drive

Application: 07/741,872 →

Intelligent Hardware for Automatically Reading and Writing Multiple Sectors of Data Between a Computer Bus and a Disk Drive

Patent: 5,768,617 →

Application: 08/153,560 →

Host Adapter Integrated Circuit Having Autoaccess Pause

Application: 08/301,461 →

Serial Port for a Host Adapter Integrated Circuit Using a Single Terminal

Application: 08/337,691 →

Dual Function Disk Drive Integrated Circuit for Master Mode and Slave Mode Operations

Patent: 5,826,093 →

Application: 08/363,448 →

Process for Balancing the Loudness of Digitally Sampled Audio Waveforms

Patent: 5,812,969 →

Application: 08/417,754 →

A Diagnostic System Including a Lsi or Vlsi Integrated Circuit with a Diagnostic Data Port

Patent: 5,764,952 →

Application: 08/450,456 →

System for Supplying Initiator Identification Information to Scsi Bus in a Reselection Phase of an Initiator Before Completion of an Autotransfer Command

Patent: 5,845,154 →

Application: 08/463,333 →

System for Storing Initiator, Queue Tag and Logical Block Information, Disconnecting from Target If Command Is Not Auto Transfer, Reconnecting and Performing Data Transfer

Patent: 5,781,803 →

Application: 08/465,075 →

Integrated Circuit with a Serial Port Having Only One Pin

Patent: 5,826,068 →

Application: 08/482,529 →

A Method of Operation of a Host Adapter Integrated Circuit

Patent: 5,838,950 →

Application: 08/486,096 →

Programmable Data Transfer Without Sector Pulses in a Headerless Disk Drive Architecture

Patent: 5,812,335 →

Application: 08/522,037 →

Hardware Alignment in a Headerless Disk Drive Architecture

Patent: 5,802,584 →

Application: 08/522,639 →

Logical and Physical Zones for Management of Defects in a Headerless Disk Drive Architecture

Patent: 5,812,755 →

Application: 08/522,687 →

System and Method for Solving Quadratic Equation in Galois Fields

Patent: 5,771,184 →

Application: 08/542,198 →

Arithmetic Logic Unit and Method for Numerical Computations in Galois Fields

Patent: 5,812,438 →

Application: 08/542,262 →

System and Method for Encoding and Decoding Data Using Numerical Computations in Galois Fields

Patent: 5,787,099 →

Application: 08/542,277 →

Apparatus for a Variable Area Nozzle

Patent: 5,782,432 →

Application: 08/571,534 →

A Serial Port Having Only a Single Terminal for Information Transfer to and from an Integrated Circuit

Patent: 5,920,708 →

Application: 08/592,800 →

Remote Procedural Call Component Management Method for a Heterogeneous Computer Network

Patent: 5,926,636 →

Application: 08/603,531 →

Method for Specifying Concurrent Execution of a String of I/O Command Blocks in a Chain Structure

Patent: 5,850,567 →

Application: 08/615,476 →

Host Adapter System Including an Integrated Pci Buffer Controller and Xor Function Circuit

Patent: 5,881,250 →

Application: 08/615,477 →

Hardware Method for Verifying That an Area of Memory Has Only Zero Values

Patent: 5,867,732 →

Application: 08/615,478 →

Method for Concurrently Executing a Configured String of Concurrent I/O Command Blocks Within a Chain Concurrently to Perform a Raid 5 I/O Operation

Patent: 5,892,969 →

Application: 08/615,479 →

Chain Manager for Use in Executing a Chain of I/O Command Blocks

Patent: 5,768,621 →

Application: 08/616,817 →

Method for Specifying Execution of Only One of a Pair of I/O Command Blocks in a Chain Structure

Patent: 5,797,034 →

Application: 08/616,836 →

Method for Enhancing Performance of a Raid 1 Read Operation Using a Pair of I/O Command Blocks in a Chain Structure

Patent: 5,758,187 →

Application: 08/616,838 →

I/O Command Block Chain Structure in a Memory

Patent: 5,812,877 →

Application: 08/616,846 →

Method for Sequencing Execution of I/O Command Blocks in a Chain Structure by Setting Hold-Off Flags and Configuring a Counter in Each I/O Command Block

Patent: 5,923,896 →

Application: 08/617,990 →

A Method of Enabling and Disabling a Data Function in an Integrated Circuit

Patent: 5,991,861 →

Application: 08/617,991 →

Digital Delay Circuit and Method

Patent: 5,789,969 →

Application: 08/617,994 →

Global Parity Symbol for Interleaved Reed-Solomon Coded Data

Patent: 5,872,799 →

Application: 08/687,009 →

Method for Determining Whether Bi-Directional or Unidirectional Data Line Circuits Are Used

Patent: 5,821,798 →

Application: 08/709,501 →

Error Generation Circuit for Testing a Digital Bus

Patent: 5,978,934 →

Application: 08/797,802 →

Format Calculator for Headerless Hard Disk with Embedded Servo Wedges

Patent: 5,959,795 →

Application: 08/808,099 →

Interleaved Burst Xor Using a Single Memory Pointer

Patent: 5,946,707 →

Application: 08/808,526 →

Method of Managing Hardware Control Blocks Utilizing Endless Queue Maintained to Never Be Empty and Containing Tail Pointer Only Accessible by Process Executing on System Processor

Patent: 6,006,292 →

Application: 08/815,645 →

Improved Hardware Command Block Delivery Queue for Host Adapters and Other Devices with Onboard Processors

Patent: 5,938,747 →

Application: 08/816,980 →

Data Sector Mark Generation for a Headerless Disk Drive Architecture

Patent: 5,940,862 →

Application: 08/823,779 →

Improved Hardware Control Block Delivery Queues for Host Adapters and Other Devices with Onboard Processors

Patent: 6,012,107 →

Application: 08/862,143 →

Host Adapter Integrated Circuit Having Autoaccess Pause

Patent: 5,960,180 →

Application: 08/869,665 →

Status Indicator for a Host Adapter

Patent: 5,978,863 →

Application: 08/876,539 →

System for Aligning Control Words for Identifying Boundaries of Headerless Data Sectors Using Automatic Incrementing and Discarding of Data Frame Numbers

Patent: 6,000,018 →

Application: 08/877,115 →

Apparatus and Method for Communication Between Integrated Circuits Connected to Each Other by a Single Line

Patent: 6,393,576 →

Application: 08/938,828 →

Integrated Pci Buffer Controller and Xor Function Circuit

Patent: 5,974,530 →

Application: 08/942,373 →

Method and Apparatus for Automatically Loading Configuration Data on Reset into a Host Adapter Integrated Circuit

Patent: 5,881,281 →

Application: 08/956,224 →

Arithmetic Logic Unit and Method for Numerical Computations in Galois Fields