IP Library Assignment 009317/0607
Patent Assignment
Reel/Frame 009317/0607

Assignment of Assignor's Interest

Recorded: 1998-06-15 Pages: 2
Assignors
FARRALL, GLENN
Executed: 1998-04-29
FEL, BRUNO
Executed: 1998-05-19
BARNABY, CATHERINE
Executed: 1998-04-29
Assignee
SGS-THOMSON MICROELECTRONICS LIMITED
ALMONDSBURY, 1000 AZTEC WEST, BRISTOL BS12 4SQ, UNITED KINGDOM
Covered Property (1)
Cache Coherency Mechanism Using an Operation to Be Executed on the Contents of a Location in a Cache Specifying an Address in Main Memory
Patent: 6,546,467 →
Application: 09/033,134 →
Publication: US 2002/0007442
Related Assignments (5)
Other recorded transfers of the patent in this record — the chain of ownership.
Change of Name Nov 16, 2015
From: SGS-THOMSON MICROELECTRONICS LIMITED
To: STMICROELECTRONICS LIMITED
Reel/Frame 037051/0053 →
Assignment of Assignor's Interest Feb 26, 2016
From: STMICROELECTRONICS LIMITED
To: STMICROELECTRONICS INTERNATIONAL NV
Reel/Frame 037879/0949 →
Assignment of Assignor's Interest Jun 23, 2016
From: STMICROELECTRONICS INTERNATIONAL NV
To: FRANCE BREVETS
Reel/Frame 039140/0584 →
Assignment of Assignor's Interest May 23, 2022
From: FRANCE BREVETS
To: MICROELECTRONIC INNOVATIONS, LLC
Reel/Frame 060161/0346 →
Corrective Assignment to Correct the the Assignee Address Previously Recorded at Reel: 060161 Frame: 0346. Assignor(S) Hereby Confirms the Assignment. Jun 16, 2022
From: FRANCE BREVETS
To: MICROELECTRONIC INNOVATIONS, LLC
Reel/Frame 060389/0768 →