Patent Assignment
Reel/Frame 010248/0305
Assignment of Assignor's Interest
Recorded: 1999-09-17
Pages: 3
Assignor
AKAOGI, TAKAO
Executed: 1999-09-08
Assignee
FUJITSU LIMITED
1-1 KAMIKODANAKA 4-CHOME, NAKAHARA-KU, KAWASAKI-SHI, KANAGAWA 211-8588, JAPAN
Covered Property
(1)
Clock Control Circuit for Generating an Internal Clock Signal with One or More External Clock Cycles Being Blocked Out and a Synchronous Flash Memory Device Using the Same
Patent:
6,104,667 →
Application:
09/365,075 →
Related Assignments
(3)
Other recorded transfers of the patent in this record — the chain of ownership.
Assignment of Assignor's Interest
Dec 12, 2008
From: FUJITSU LIMITED
To: FUJITSU MICROELECTRONICS LIMITED
Reel/Frame 021965/0746 →
Change of Name
Jun 25, 2010
From: FUJITSU MICROELECTRONICS LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 024597/0507 →
Assignment of Assignor's Interest
Apr 27, 2015
From: FUJITSU SEMICONDUCTOR LIMITED
To: SOCIONEXT INC.
Reel/Frame 035508/0637 →