Patent Assignment
Reel/Frame 010763/0572
Assignment of Assignor's Interest
Recorded: 2000-05-02
Pages: 14
Assignor
MICRON ELECTRONICS, INC.
Executed: 2000-03-17
Assignee
MICRON TECHNOLOGY, INC.
8000 S. FEDERAL WAY, BOISE, IOWA, 83716
Covered Properties
(160)
Method and System for Apportioning Computer Bus Bandwidth
Patent:
5,740,380 →
Application:
08/680,464 →
System and Method for Memory Error Handling
Patent:
5,905,858 →
Application:
08/742,773 →
System and Method for Identification of Computer Data Storage Devices
Application:
08/756,171 →
Memory Fault Correction System and Method
Patent:
6,076,182 →
Application:
08/767,180 →
Method and System for Avoiding Livelock Conditions on a Computer Bus by Insuring That the First Retired Bus Master Is the First to Resubmit Its Retired Transaction
Patent:
6,141,715 →
Application:
08/826,548 →
Memory Controller with Buffered Cas/Ras External Synchronization Capability for Reducing the Effects of Clock-to-Signal Skew
Patent:
6,044,474 →
Application:
08/826,827 →
System for Communicating Through a Computer System Bus Bridge
Patent:
6,047,349 →
Application:
08/873,994 →
Method for Testing a Controller with Random Constraints
Patent:
6,076,180 →
Application:
08/880,351 →
Gart and Ptes Defined by Configuration Registers
Patent:
6,249,853 →
Application:
08/882,054 →
Gart and Pites Defined by Configurat Ion Registers
Patent:
6,282,625 →
Application:
08/882,327 →
System for Accelerated Graphics Port Address Remapping Interface to Main Memory
Patent:
6,069,638 →
Application:
08/882,428 →
System for Implementing a Graphic Address Remapping Table as a Virtual Register File in System Memory
Patent:
6,195,734 →
Application:
08/886,525 →
Method of Processing Memory Transactions in a Computer System Having Dual System Memories and Memory Controllers
Patent:
6,202,133 →
Application:
08/887,041 →
A Segmented Memory System Employing Different Interleaving Scheme for Each Different Memeory Segment
Patent:
6,049,855 →
Application:
08/887,042 →
Method for Implementing a Graphic Address Remapping Table as a Virtual Register File in System Memory
Patent:
6,192,457 →
Application:
08/887,868 →
System and Method for Invalidating Cache Memory
Patent:
6,378,047 →
Application:
08/888,501 →
Dynamic Buffer Allocation for a Computer System
Patent:
6,243,769 →
Application:
08/896,936 →
System for Dynamic Buffer Allocation Comprising Control Logic for Controlling a First Address Buffer and a First Data Buffer as a Matched Pair
Patent:
6,073,190 →
Application:
08/896,938 →
Hierarchical Bus Struture Access System
Patent:
6,078,977 →
Application:
08/922,243 →
Variable Speed Controller
Patent:
6,047,381 →
Application:
08/925,885 →
Method for Improving Data Transfer Rates for User Data Stored on a Disk Storage Device
Patent:
6,026,463 →
Application:
08/927,233 →
Inter-Module Data Management Methodology for Circuit Synthesis
Patent:
6,098,068 →
Application:
08/951,993 →
Bi-Directional Synchronizing Buffer System
Patent:
6,055,597 →
Application:
08/960,777 →
Method for Providing Additional Latency for Synchronously Accessed Memory
Patent:
6,185,664 →
Application:
08/971,834 →
Solid Pack Fish Canning Machine
Patent:
5,887,414 →
Application:
08/971,973 →
Method for Configuring Peer-to-Peer Bus Bridges in a Computer System Using Shadow Configuration Registers
Application:
08/974,374 →
Method for Use of Bus Parking States to Communicate Diagnostic Information
Patent:
6,092,219 →
Application:
08/984,115 →
System for Use of Bus Parking States to Communicate Diagnostic Information
Patent:
6,112,316 →
Application:
08/984,393 →
Method for Providing Two Modes of I/O Pad Termination
Patent:
6,040,714 →
Application:
08/990,057 →
Accelerated Graphics Port for Multiple Memory Controller Computer System
Patent:
6,252,612 →
Application:
09/000,511 →
Method of Implementing an Accelarated Graphics Port for a Multiple Memory Controller Computer System
Patent:
6,157,398 →
Application:
09/000,517 →
System for Issuing Device Requests by Proxy
Patent:
6,301,645 →
Application:
09/008,899 →
Method for Extending the Available Number of Configuration Registers
Patent:
6,108,733 →
Application:
09/008,966 →
System for Extending the Available Number of Configuration Registers
Patent:
6,243,775 →
Application:
09/008,973 →
Method for Identifying the Original Source Device in a Transaction Request Initiated from Address Translator to Memory Control Module and Directly Performing the Transaction Therebetween
Patent:
6,067,581 →
Application:
09/008,974 →
A Method for Configuring Memory to Reduce Latency
Patent:
6,397,299 →
Application:
09/009,911 →
Apparatus for Increasing the Number of Loads Supported by a Host Bus
Patent:
6,263,389 →
Application:
09/009,915 →
A Method for Increasing the Number of Devices Capable of Being Operably Connected to a Host Bus
Patent:
6,041,380 →
Application:
09/010,084 →
System Controller with Integrated Low Latency Memory
Application:
09/010,250 →
Programmable Logic Block in an Integrated Circuit
Patent:
6,075,381 →
Application:
09/010,335 →
Method for Modifying an Integrated Circuit
Patent:
6,209,118 →
Application:
09/010,337 →
Method and System for Apportioning Computer Bus Bandwith
Patent:
6,058,450 →
Application:
09/016,055 →
Method for Terminating a Processor Bus
Patent:
6,128,685 →
Application:
09/025,388 →
Device for Terminating a Processor Bus
Patent:
6,122,695 →
Application:
09/025,722 →
Method of Shortening Boot Up Time in a Computer System
Patent:
6,122,677 →
Application:
09/045,974 →
System for Configuring Peer Devices
Patent:
6,233,638 →
Application:
09/045,975 →
Apparatus for Assisting Video Compression in a Computer System
Patent:
6,987,545 →
Application:
09/048,932 →
Method for Assisting Video Compression in a Computer System
Method of Peer-to-Peer Mastering Over a Computer Bus
Patent:
6,223,238 →
Application:
09/053,378 →
System for Peer-to-Peer Mastering Over a Computer Bus
Patent:
6,073,198 →
Application:
09/053,392 →
Method for Blocking Bus Transactions During Reset
Patent:
6,134,656 →
Application:
09/056,197 →
Device for Blocking Bus Transactions During Reset
Patent:
6,108,778 →
Application:
09/056,198 →
System for Autonomous Configuration of Peer Devices
Method for Autonomous Configuration of Peer Devices
Patent:
6,266,770 →
Application:
09/060,099 →
Verification of Sensitivity List Integrity in a Hardware Description Language File
Patent:
6,367,064 →
Application:
09/083,716 →
Method for Read Only Memory Shadowing
Patent:
6,216,224 →
Application:
09/092,460 →
Method for Time Multiplexing a Low-Speed and a High-Speed Bus Over Shared Signal Lines of a Physical Bus
Patent:
6,311,245 →
Application:
09/092,585 →
Time-Multiplexed Multi-Speed Bus
Patent:
6,425,041 →
Application:
09/092,586 →
System for Read Only Memory Shadowing Circuit for Copying a Quantity of Rom Data to the Ram Prior to Initialization of the Computer System
Patent:
6,330,667 →
Application:
09/092,588 →
Computer System Having a Plurality of Bus Agents Coupled to Bus Requesters Wherein Each Bus Agent Includes an Internal Arbiter That Selects One of the Bus Requests
Patent:
6,347,352 →
Application:
09/093,579 →
Method for Adaptive Decoding of Memory Addresses
Patent:
6,260,121 →
Application:
09/106,967 →
Apparatus for Adaptive Decoding of Memory Addresses
Patent:
6,253,276 →
Application:
09/107,782 →
System and Method for Remapping Defective Memory Locations
Patent:
6,052,798 →
Application:
09/108,572 →
Verification of Port List Integrity in a Hardware Description Language File
Patent:
6,237,007 →
Application:
09/110,083 →
Method for Decoding Addresses
Patent:
6,349,376 →
Application:
09/111,243 →
Method for Determining Status of Multiple Interlocking Fifo Buffer Structures Based on the Position of at Least One Pointer of Each of the Multiple Fifo Buffers
Patent:
6,243,770 →
Application:
09/119,663 →
Sequential Data Transfer Method
Patent:
6,088,812 →
Application:
09/119,763 →
Sequential Data Transfer Circuit
Patent:
6,163,819 →
Application:
09/119,979 →
Method for Sharing Data Buffers from a Buffer Pool
Patent:
6,161,153 →
Application:
09/126,942 →
System for Sharing Data Buffers from a Buffer Pool
Patent:
6,282,589 →
Application:
09/126,978 →
Pipelined Memory Controller
Patent:
6,272,609 →
Application:
09/127,207 →
Method of Processing Memory Requests in a Pipelined Memory Controller
Patent:
6,295,592 →
Application:
09/127,282 →
Memory Paging Control Method
Patent:
6,219,764 →
Application:
09/128,403 →
Memory Paging Control Apparatus
Patent:
6,219,765 →
Application:
09/128,410 →
Bus Modeling Language Generator
Patent:
6,571,204 →
Application:
09/128,704 →
Processor with Internal Register for Peripheral Status
Patent:
6,233,627 →
Application:
09/131,446 →
Core Logic Unit with Internal Register for Peripheral Status
Patent:
6,219,720 →
Application:
09/131,447 →
Method for Operating Processor with Internal Register for Peripheral Status
Patent:
6,189,049 →
Application:
09/131,497 →
Method for Operating Core Logic Unit with Internal Register for Peripheral Status
Local Bus Interface
Patent:
6,061,510 →
Application:
09/149,689 →
Method of Processing System Management Interrupt Requests
Patent:
6,145,048 →
Application:
09/153,992 →
Computer System for Processing System Management Interrupt Requests
Patent:
6,212,592 →
Application:
09/156,182 →
Upgradeable Cache Circuit Using High Speed Multiplexer
Patent:
6,219,755 →
Application:
09/158,169 →
Method for Providing and Operating Upgradeable Cache Circuitry (as Amended)
Patent:
6,119,197 →
Application:
09/158,179 →
A Method for Prioritizing Data Transfer Request by Comparing a Latency Indentifier Value Received from an I/O Device with a Perdetermined Range of Values
Patent:
6,304,923 →
Application:
09/172,923 →
Apparatus for Controlling Data Transfer Operations Between a Memory and Devices Having Respective Latencies
Patent:
6,266,718 →
Application:
09/172,926 →
Method of Bus Arbitration Using Requesting Device Bandwidth and Priority Ranking
Patent:
6,363,445 →
Application:
09/173,573 →
Graphics Controller Embedded in a Core Logic Unit
Patent:
6,346,946 →
Application:
09/177,739 →
Processing System with Separate General Purpose Execution Unit and Data String Manipulation Unit
Patent:
6,658,552 →
Application:
09/178,196 →
Method for Providing Graphics Controller Embedded in a Core Logic Unit
Method for Controlling a Direct Mapped or Two Way Set Associative Cache Memory in a Computer System
Apparatus for Aligning Clock and Data Signals Received from a Ram
Patent:
6,101,612 →
Application:
09/183,627 →
Method for Aligning Clock and Data Signals Received from a Ram
Patent:
6,108,795 →
Application:
09/183,781 →
Circuit Synthesis Time Budgeting Based Upon Wireload Information
Patent:
6,233,724 →
Application:
09/183,782 →
Placing Gates in an Integrated Circuit Based Upon Drive Strength
Patent:
6,233,722 →
Application:
09/189,566 →
System and Method for Reducing Latency in Software Modem for High- -Speed Synchronous Transmission
Patent:
6,233,250 →
Application:
09/191,569 →
Fifth Wheel Hitch Bumper
Patent:
6,158,758 →
Application:
09/191,571 →
Apparatus for Controlling Refresh of a Multibank Memory Device
Patent:
6,298,413 →
Application:
09/196,571 →
Controlling a Paging Policy Based on a Requestor Characteristic
Patent:
6,199,138 →
Application:
09/200,622 →
System for Memory Error Handling
Patent:
6,085,339 →
Application:
09/201,277 →
Providing Device Status During Bus Retry Operations
Patent:
6,240,473 →
Application:
09/201,410 →
Controlling a Paging Policy Based on a Requestor Characteristic
Patent:
6,212,598 →
Application:
09/201,456 →
Method for Storing Device Status in a Target Device and Providing the Stored Device Status During Bus Retry Operations
Patent:
6,324,596 →
Application:
09/201,550 →
Apparatus for Receiving Data from a Synchronous Random Access Memory
Patent:
6,163,852 →
Application:
09/206,454 →
Method for Receiving Data from a Synchronous Random Access Memory
Patent:
6,181,638 →
Application:
09/206,793 →
Method for Controlling Pipelined Memory Access Requests
Patent:
6,292,807 →
Application:
09/212,047 →
Apparatus for Controlling Pipelined Memory Access Requests
Patent:
6,321,233 →
Application:
09/212,139 →
Method for Controlling Out of Order Accessing to a Multibank Memory
Programmable Graphics Memory Method
Patent:
6,414,688 →
Application:
09/239,633 →
Method to Access Memory Based on a Programmable Page Limit
Programmable Graphics Memory Apparatus
Patent:
6,377,268 →
Application:
09/240,514 →
Device to Access Memory Based on a Programmable Page Limit
Patent:
6,408,371 →
Application:
09/240,526 →
Method for Multiplexing Bus Interfaces on a Computer Expansion Bus
Patent:
6,430,637 →
Application:
09/244,371 →
Apparatus for Multiplexing Bus Interfaces on a Computer Expansion Bus
Patent:
6,370,593 →
Application:
09/244,598 →
Apparatus for Configuring Devices on a Communications Channel
Patent:
6,507,879 →
Application:
09/248,559 →
Method of Configuring Devices on a Communications Channel
Patent:
6,549,963 →
Application:
09/248,598 →
Apparatus for Enabling System Operation
Patent:
6,256,180 →
Application:
09/258,230 →
Method of Enabling System Operation
Patent:
6,275,364 →
Application:
09/258,236 →
Bidirectional Data Transfer During Buffer Flushing Operations
Patent:
6,513,090 →
Application:
09/283,335 →
Detecting CYP24 Expression Level as a Marker for Predisposition to Cancer
Patent:
7,648,826 →
Application:
09/285,292 →
Technique to Automatically Notify an Operating System Level Application of a System Management Event
Patent:
6,463,492 →
Application:
09/289,151 →
Apparatus for Automatically Notifying Operating System Level Applications of the Occurrence of System Management Events
Patent:
6,321,289 →
Application:
09/289,152 →
Agp Clock Start/Stop Detection Circuit
Patent:
6,418,502 →
Application:
09/324,397 →
Functional Level Configuration of Input-Output Test Circuitry
Patent:
6,453,448 →
Application:
09/327,278 →
Apparatus for Multiplexing Signals
Patent:
6,697,387 →
Application:
09/327,284 →
Method for Multiplexing Signals Through I/O Pins
Patent:
6,678,287 →
Application:
09/327,291 →
Method for Configuring Bus Architecture Through Software Control
Patent:
6,401,151 →
Application:
09/327,412 →
Apparatus for Configuring Bus Architecture Through Software Control
Patent:
6,425,029 →
Application:
09/327,413 →
Method for Selectively Encoding Bus Grant Lines to Reduce I/O Pin Requirements
Patent:
6,363,446 →
Application:
09/332,278 →
Apparatus for Selectively Encoding Bus Grant Lines to Reduce I/O Pin Requirements
Patent:
6,363,447 →
Application:
09/332,279 →
Mechanism to Expand Address Space of a Serial Bus
Patent:
6,526,464 →
Application:
09/349,422 →
Timing Circuit for High Speed Memory
Patent:
6,401,213 →
Application:
09/349,816 →
Method for Synchronizing Strobe and Data Signals from a Ram
Patent:
6,453,402 →
Application:
09/352,718 →
Apparatus for Synchronizing Strobe and Data Signals Received from a Ram
Patent:
6,629,222 →
Application:
09/352,719 →
Apparatus for Supporting Multiple Delayed Read Transactions Between Computer Buses
Patent:
6,385,686 →
Application:
09/352,720 →
Method for Supporting Multiple Delayed Read Transactions Between Computer Buses
Patent:
6,381,667 →
Application:
09/352,721 →
Method for Providing Fast Memory Decode Using a Bank Conflict Table
Patent:
6,425,043 →
Application:
09/352,722 →
Apparatus for Providing Fast Memory Decode Using a Bank Conflict Table
Patent:
6,425,044 →
Application:
09/352,723 →
Bus Arbitration
Patent:
6,654,833 →
Application:
09/363,547 →
System and Method for Regulating Data Capture in Response to Data Strobe Using Preamble, Postamble and Strobe Signature
Patent:
6,615,345 →
Application:
09/363,594 →
Reducing Memory Latency by Not Performing Bank Conflict Checks on Idle Banks
Patent:
6,266,734 →
Application:
09/363,604 →
Capturing Read Data
Patent:
6,763,416 →
Application:
09/363,605 →
Storing a Flushed Cache Line in a Memory Buffer of a Controller
Adjusting and Measuring the Timing of a Data Strobe Signal with a First Delay Line and Through Additional Delay Line Adapted to Receive Pulse Signal
Patent:
6,467,043 →
Application:
09/363,790 →
Apparatus and Method for Automatically Selecting an Appropriate Signal from a Plurality of Signals, Based on the Configuration of a Peripheral Installed Within a Computing Device
Patent:
6,510,473 →
Application:
09/378,560 →
Method for Testing a Controller with Random Constraints
Patent:
6,535,841 →
Application:
09/383,169 →
Memory Cache with Sequential Page Indicators
Patent:
6,330,654 →
Application:
09/383,468 →
Enhanced Bus Connectivity Through Distributed Loading
Patent:
6,636,920 →
Application:
09/384,665 →
Bus to System Memory Delayed Read Processing
Memory Bandwidth Allocation Based on Access Count Priority Scheme
Patent:
6,330,647 →
Application:
09/386,973 →
Method and Apparatus for an Adjustable Delay Circuit Having Arranged Serially Coarse Stages Received by a Fine Delay Stage
Patent:
6,795,931 →
Application:
09/409,367 →
Method and Apparatus to Reduce Memory Read Latency
Patent:
6,321,315 →
Application:
09/409,523 →
Method and Apparatus for Providing Visibility and Control Over Components Within a Programmable Logic Circuit for Emulation Purposes
Patent:
6,421,813 →
Application:
09/417,964 →
Apparatus for Flexibly Allocating Request/Grant Pins Between Multiple Bus Controllers
Patent:
6,389,492 →
Application:
09/418,465 →
Method for Preserving Memory Request Ordering Across Multiple Memory Controllers
Patent:
6,275,913 →
Application:
09/418,466 →
Apparatus for Preserving Memory Request Ordering Across Multiple Memory Controllers
Patent:
6,275,914 →
Application:
09/418,467 →
Method for Flexibly Allocating Request/Grant Pins Between Multiple Bus Controllers
Patent:
6,385,680 →
Application:
09/418,468 →
Method and Device to Use Memory Access Request Tags
Computer System Having Reduced Number of Bus Bridge Terminals
Patent:
6,591,318 →
Application:
09/490,771 →
Method of Initializing a Processor and Computer System
Patent:
6,654,832 →
Application:
09/493,441 →
Related Assignments
(25)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Sep 30, 1996
From: LABERGE, PAUL A.; JEDDELOH, JOE; PORTERFIELD, A. KENT
To: MICRON ELECTRONICS, INC.
Reel/Frame 008187/0369 →
Assignment of Assignor's Interest
Nov 1, 1996
From: JEDDELOH, JOSEPH
To: MICRON ELECTRONICS, INC.
Reel/Frame 008302/0152 →
Assignment of Assignor's Interest
Nov 25, 1996
From: KLEIN, DEAN A.
To: MICRON ELECTRONICS, INC.
Reel/Frame 008338/0611 →
Assignment of Assignor's Interest
Dec 16, 1996
From: JEDDELOH, JOSEPH
To: MICRON ELECTRONICS, INC.
Reel/Frame 008351/0834 →
Assignment of Assignor's Interest
Apr 3, 1997
From: PORTERFIELD, A. KENT
To: MICRON ELECTRONICS, INC.
Reel/Frame 008653/0934 →
Assignment of Assignor's Interest
Oct 10, 1997
From: ROONEY, JEFFREY JAY
To: MICRON ELECTRONICS, INC.
Reel/Frame 008751/0109 →
Assignment of Assignor's Interest
Oct 10, 1997
From: ROONEY, JEFFREY JAY
To: MICRON ELECTRONICS, INC.
Reel/Frame 008760/0439 →
Assignment of Assignor's Interest
Oct 20, 1997
From: MEYER, JAMES W.
To: MICRON ELECTRONICS, INC.
Reel/Frame 008759/0772 →
Assignment of Assignor's Interest
Oct 20, 1997
From: ROONEY, JEFFREY JAY
To: MICRON ELECTRONICS, INC.
Reel/Frame 008796/0971 →
Assignment of Assignor's Interest
Jan 5, 1998
From: KLEIN, DEAN A.
To: MICRON ELECTRONICS, INC.
Reel/Frame 008916/0073 →
Assignment of Assignor's Interest
Jan 12, 1998
From: PORTERFIELD, A. KENT
To: MICRON ELECTRONICS, INC.
Reel/Frame 008902/0869 →
Assignment of Assignor's Interest
Jan 12, 1998
From: PORTERFIELD, A. KENT
To: MICRON ELECTRONICS, INC.
Reel/Frame 008904/0690 →
Assignment of Assignor's Interest
Jan 23, 1998
From: JEDDELOH, JOSEPH
To: MICRON ELECTRONICS, INC.
Reel/Frame 009073/0810 →
Assignment of Assignor's Interest
Jan 26, 1998
From: JEDDELOH, JOSEPH
To: MICRON ELECTRONICS, INC.
Reel/Frame 008972/0742 →
Assignment of Assignor's Interest
Jan 29, 1998
From: PORTERFIELD, A. KENT
To: MICRON ELECTRONICS, INC.
Reel/Frame 008949/0355 →
Assignment of Assignor's Interest
Jan 29, 1998
From: PORTERFIELD, A. KENT
To: MICRON ELECTRONICS, INC.
Reel/Frame 008949/0538 →
Assignment of Assignor's Interest
Feb 9, 1998
From: PORTERFIELD, A. KENT
To: MICRON ELECTRONICS, INC.
Reel/Frame 009004/0944 →
Assignment of Assignor's Interest
Feb 20, 1998
From: BROWN, JEFFREY R.
To: MICRON ELECTRONICS, INC.
Reel/Frame 008987/0765 →
Assignment of Assignor's Interest
Mar 9, 1998
From: HOUG, TODD C.
To: MICRON ELECTRONICS, INC.
Reel/Frame 009035/0214 →
Assignment of Assignor's Interest
Mar 16, 1998
From: KLEIN, DEAN A.
To: MICRON ELECTRONICS, INC.
Reel/Frame 009047/0842 →
Assignment of Assignor's Interest
Mar 20, 1998
From: JEDDELOH, JOSEPH M.
To: MICRON ELECTRONICS,INC.
Reel/Frame 009054/0260 →
Assignment of Assignor's Interest
May 4, 1998
From: KLEIN, DEAN A.
To: MICRON ELECTRONICS, INC.
Reel/Frame 009151/0443 →
Assignment of Assignor's Interest
May 11, 1998
From: ROWLEY, EDWARD J.; GORBY, JACK
To: LUTHI MACHINERY & ENGINEERING CO., INC.
Reel/Frame 009166/0359 →
Assignment of Assignor's Interest
May 11, 1998
From: MEYER, JAMES W.
To: MICRON ELECTRONICS, INC.
Reel/Frame 009181/0732 →
Assignment of Assignor's Interest
May 11, 1998
From: KLEIN, DEAN A.
To: MICRON ELECTRONICS, INC.
Reel/Frame 009195/0631 →