Patent Assignment
Reel/Frame 011460/0061
Assignment of Assignor's Interest
Recorded: 2001-01-16
Received: 2001-01-30
Pages: 3
Assignors
ARIMOTO, KAZUTAMI
Executed: 2000-12-20
FURUBEPPU, SEIZOU
Executed: 2000-12-20
ISHIZUKA, YASUHIRO
Executed: 2000-12-20
SHIMANO, HIROKI
Executed: 2000-12-20
SUGANO, HIROKI
Executed: 2000-12-20
Assignees
MITSUBISHI DENKI KABUSHIKI KAISHA
2-3, MARUNOUCHI 2-CHOME, CHIYODA-KU, TOKYO 100-8310, JPX, JAPAN
MITSUBISHI ELECTRIC ENGINEERING COMPANY LIMITED
6-2, OOTEMACHI 2-CHOME, CHIYODA-KU, TOKYO 100-0004, JPX, JAPAN
Covered Property
(1)
Semiconductor Merged Logic and Memory Capable of Preventing an Increase in an Abnormal Current During Power-Up
Application:
09/759,315 →