Patent Assignment
Reel/Frame 011498/0122
Assignment of Assignor's Interest
Recorded: 2001-01-23
Received: 2001-02-12
Pages: 6
Assignors
MATTHEWS, DENNIS
Executed: 2000-01-03
TRAUNER, KENNETH
Executed: 2000-01-05
HADDAD, WALEED
Executed: 2000-01-13
KLUIWSTRA, JAN-ULCO
Executed: 2000-12-20
CHANG, JOHN
Executed: 2000-12-21
Assignee
REGENTS OF THE UNIVERSITY OF CALIFORNIA, THE
1111 FRANKLIN STREET, OAKLAND, CA, 94612, UNITED STATES
Covered Properties
(5)
Method and Apparatus for Testing Semiconductor Integrated Circuit, and Semiconductor Integrated Circuit Manufactured Thereby
Application:
09/766,845 →
Three-Dimensional Graphic Processing Device for Drawing Polygon Having Vertex Data Defined by Relative Value and Method Therefor
Application:
09/766,840 →
Printer Image Processing System with Customized Tone Reproduction Curves
Application:
09/767,938 →
Semiconductor Device with Transfer Gate Having Gate Insulating Film and Gate Electrode Layer
Application:
09/766,846 →
Ultrasound Image Guided Acetabular Implant Orientation During Total Hip Replacement
Application:
09/767,454 →