Assignment of Assignor's Interest

Recorded: 2001-10-15 Received: 2001-10-22 Pages: 2

Assignors

TERAMOTO, AKINOBU

Executed: 2001-09-17

TERAUCHI, TAKASHI

Executed: 2001-09-17

Assignee

CHIYODA-KU, 2-3, MARUNOUCHI 2-CHOME, TOKYO 100-8310, JPX, JAPAN

Covered Properties (2)

Method of Manufacturing Semiconductor Device, and Semiconductor Device Having Memory Cell

Application: 09/976,341 →

Integrated Circuit Package Via

Application: 09/975,871 →