Patent Assignment
Reel/Frame 012267/0540
Assignment of Assignor's Interest
Recorded: 2001-10-10
Pages: 2
Assignors
SAZE, TAKUYA
Executed: 2001-10-05
TAMURA, HIROTAKA
Executed: 2001-10-05
CHIBA, TAKAYA
Executed: 2001-10-05
GOTOH, KOHTAROH
Executed: 2001-10-05
ISHIDA, HIDEKI
Executed: 2001-10-05
Assignee
FUJITSU LIMITED
NAKAHARA-KU, 1-1, KAMIKODANAKA 4-CHOME, KAWASAKI-SHI, KANAGAWA 211-8588, JAPAN
Covered Property
(1)
Clock Recovery Circuit and Receiver Circuit for Improving the Error Rate of Signal Reproduction
Related Assignments
(1)
Other recorded transfers of the patent in this record — the chain of ownership.