IP Library › Assignment 012415/0370
Patent Assignment
Reel/Frame 012415/0370

Assignment of Assignor's Interest

Recorded: 2002-01-03 Pages: 5
Assignor
JARVIS, ANTHONY X.
Executed: 2001-03-16
Assignee
STMICROELECTRONICS, INC.
1310 ELECTRONICS DRIVE, CARROLLTON, TEXAS, 75006
Covered Property (1)
System and Method for Executing Variable Latency Load Operations in a Date Processor
Patent: 7,757,066 →
Application: 09/751,372 →
Publication: US 2002/0087839
Related Assignments (4)
Other recorded transfers of the patent in this record — the chain of ownership.
Assignment of Assignor's Interest May 7, 2001
From: JARVIX, ANTHONY X.
To: STMICROELECTRONICS, INC.
Reel/Frame 011769/0373 →
Assignment of Assignor's Interest Aug 2, 2001
From: FARABOSCHI, PAOLO
To: HEWLETT-PACKARD COMPANY
Reel/Frame 012044/0363 →
Assignment of Assignor's Interest Sep 1, 2015
From: HEWLETT-PACKARD COMPANY
To: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
Reel/Frame 036518/0623 →
Assignment of Assignor's Interest Nov 9, 2015
From: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
To: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Reel/Frame 037079/0001 →