Patent Assignment
Reel/Frame 014964/0218
Security Agreement
Recorded: 2004-02-09
Received: 2004-02-13
Pages: 6
Assignor
VIRTUAL SILICON TECHNOLOGY, INC.
Executed: 2003-09-22
Assignee
SILICON VALLEY BANK
3003 TASMAN DR., LOAN DOCUMENTATION HA155, SANTA CLARA, CA, 95054, UNITED STATES
Covered Properties
(4)
Sram Bit Line Architecture
Application:
10/310,745 →
Control Circuitry for a Non-Volatile Memory
Application:
10/247,767 →
Integrated Circuit Having a Reduced Spacing Between a Bus and Adjacent Circuitry
Application:
10/245,794 →
Common Source Eeprom and Flash Memory
Application:
10/002,607 →