IP Library Assignment 016066/0818
Patent Assignment
Reel/Frame 016066/0818

Assignment of Assignor's Interest

Recorded: 2004-12-08 Pages: 3
Assignors
YOSHIDA, TAKAKI
Executed: 2004-11-08
OCHI, KEISUKE
Executed: 2004-11-08
Assignee
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
1006, OAZA KADOMA, KADOMA-SHI, OSAKA, 571-8501, JAPAN
Covered Property (1)
Semiconductor Integrated Circuit Verification Method and Test Pattern Preparation Method
Patent: 7,484,166 →
Application: 11/006,669 →
Publication: US 2005/0149790
Related Assignments (1)
Other recorded transfers of the patent in this record — the chain of ownership.
Change of Name Nov 24, 2008
From: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
To: PANASONIC CORPORATION
Reel/Frame 021897/0653 →