IP Library › Assignment 016420/0016
Patent Assignment
Reel/Frame 016420/0016

Assignment of Assignor's Interest

Recorded: 2005-03-18 Pages: 2
Assignors
NAKAJIMA, TSUTOMU
Executed: 2004-08-06
YOSHIDA, KEIICHI
Executed: 2004-08-20
Assignee
RENESAS TECHNOLOGY CORP.
4-1, MARUNOUCHI 2-CHOME, CHIYODA-KU, TOKYO, JAPAN
Covered Property (1)
Optimized Layout for Multi-Bit Memory Banks Each with Two Data Latches and Two Arithmetic Circuits
Patent: 7,233,523 →
Application: 10/503,619 →
Publication: US 2005/0157548
Related Assignments (3)
Other recorded transfers of the patent in this record — the chain of ownership.
Change of Name Aug 13, 2010
From: NEC ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 024864/0635 →
Merger Aug 13, 2010
From: RENESAS TECHNOLOGY CORP.
To: NEC ELECTRONICS CORPORATION
Reel/Frame 024879/0190 →
Change of Address Nov 29, 2017
From: RENESAS ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 044928/0001 →