Patent Assignment
Reel/Frame 016547/0979
Retroactive Assignment and Quitclaim
Recorded: 2005-09-20
Received: 2005-09-20
Pages: 8
Assignors
BARBIER, JEAN
Executed: 2005-08-26
BEDOISEAU, FLORENT
Executed: 2005-08-26
BURGUN, LUC M.
Executed: 2005-08-26
DAVIS, ROBERT W.
Executed: 2005-08-26
DIEHL, PHILIPPE
Executed: 2005-08-26
DOUEZY, FRANCOIS
Executed: 2005-08-26
EMIRIAN, FREDERIC M.
Executed: 2005-08-26
FILOCHE, OLIVIER
Executed: 2005-08-26
HOCHAPFEL, ERIC G.F.
Executed: 2005-08-26
JOSSO, FREDERIC
Executed: 2005-08-26
LAURENT, GILLES
Executed: 2005-08-26
LEPAPE, OLIVIER
Executed: 2005-08-26
MAQUINON, FRANCK
Executed: 2005-08-26
MARANTZ, JOSHUA D.
Executed: 2005-08-26
META SYSTEMS SARL
Executed: 2005-08-26
MONTAGNE, XAVIER
Executed: 2005-08-26
QUENNESSON, CYRIL
Executed: 2005-08-26
RAYNAUD, ALAIN
Executed: 2005-08-26
REBLEWSKI, FREDERIC
Executed: 2005-08-26
SAINT GENIEYS, DAVID FENECH
Executed: 2005-08-26
SCHMITT, PEER G.
Executed: 2005-08-26
SELVIDGE, CHARLEY
Executed: 2005-08-26
Assignees
MENTOR GRAPHICS CORPORATION
8005 SW BOECKMAN ROAD, WILSONVILLE, OR, 97070-7777, UNITED STATES
MENTOR GRAPHICS (HOLDING) LTD.
8005 SW BOECKMAN DRIVE, WILSONVILLE, OR, 97070-7777, UNITED STATES
Covered Properties
(23)
Data Compaction and Pin Assignment
PCT:
PCTUS2004019433 ↗
Logic Design Modeling and Interconnection
Application:
10/824,489 →
Reconfigurable integrated circuit with integrated debugging facilities and scalable programmable interconnect
Application:
10/806,235 →
Ternary Bit Line Signaling
Application:
10/791,834 →
Tester Channel Count Reduction Using Observe Logic and Pattern Generator
Application:
10/782,410 →
Distributed Configuration of Integrated Circuits in an Emulation System
Application:
10/736,908 →
Testing of Reconfigurable Logic and Interconnect Sources
Application:
10/673,211 →
Regionally Time Multiplexed Emulation System
Application:
10/668,236 →
Configuration of Reconfigurable Interconnect Portions
Application:
10/631,824 →
Data compaction and pin assignment
Application:
10/602,020 →
Reconfigurable logic element with input swapping
Application:
10/460,701 →
Emulation of Circuits with in-Circuit Memory
Application:
10/458,176 →
Compression of Emulation Trace Data
Application:
10/454,818 →
Integrated self-testing of a reconfigurable interconnect
Application:
10/428,917 →
Method and Apparatus for Concurrent Emulation of Multiple Circuit Designs on an Emulation System
Application:
10/273,700 →
Control Circuitry for a Non-Volatile Memory
Application:
10/247,767 →
Integrated Circuit Having a Reduced Spacing Between a Bus and Adjacent Circuitry
Application:
10/245,794 →
Reconfigurable Integrated Circuit with Integrated Debugging Facilities and Scalable Programmable Interconnect
Application:
10/086,813 →
Emulation components and system including distributed trace data collection and pre-processing
Application:
10/001,070 →
Common Source Eeprom and Flash Memory
Application:
10/002,607 →
Emulation Components and System Including Distributed Event Monitoring, and Testing of an Ic Design Under Emulation
Application:
10/003,184 →
Emulation Components and System Including Distributed Routing and Configuration of Emulation Resources
Application:
10/003,951 →
Cross Function Block Partitioning and Placement of a Circuit Design Onto Reconfigurable Logic Devices
Application:
09/901,780 →