Patent Assignment
Reel/Frame 017025/0832
MERGER
Recorded: 2006-01-18
Received: 2006-01-18
Pages: 4
Assignor
CICADA SEMICONDUCTOR CORPORATION
Executed: 2005-09-26
Assignee
VITESSE SEMICONDUCTOR CORPORATION
741 CALLE PLANO, CAMARILLO, CA, 93012, UNITED STATES
Covered Applications
(14)
RESERVE BATTERY WITH SET BACK MECHANISM FOR DELAYED BATTERY ACTIVATION
App. No. 10/924,000
→
BATTERY WITH COMPLETE DISCHARGE DEVICE
App. No. 10/792,367
→
OUTPUT CLOCK ADJUSTMENT FOR A DIGITAL I/O BETWEEN PHYSICAL LAYER DEVICE AND MEDIA ACCESS CONTROLLER
App. No. 10/754,204
→
SWITCHING MODE REGULATOR FOR SFP ETHERNET ADAPTOR
App. No. 10/754,250
→
METHOD FOR DETECTING LINK PARTNER STATE DURING AUTO NEGOTIATION AND SWITCHING LOCAL STATE TO ESTABLISH LINK
App. No. 10/754,256
→
Multi-channel line interface unit with on-chip clock management
App. No. 10/462,214
→
Channel status management system for multi-channel LIU
App. No. 10/462,213
→
ON-CHIP CALIBRATED SOURCE TERMINATION FOR VOLTAGE MODE DRIVER AND METHOD OF CALIBRATION THEREOF
App. No. 10/411,993
→
AUTOCLAVABLE BATTERY PACK
App. No. 10/287,727
→
TRANSFORMERLESS ETHERNET CONTROLLER
App. No. 10/189,619
→
BATTERY CHARGER AND CHARGE CONTROL SYSTEM
App. No. 10/051,402
→
OUTPUT DRIVER FOR HIGH SPEED ETHERNET TRANSCEIVER
App. No. 09/894,388
→
REDUCED GMII WITH INTERNAL TIMING COMPENSATION
App. No. 09/870,394
→
PAD CALIBRATION CIRCUIT WITH ON-CHIP RESISTOR
App. No. 09/850,530
→