Patent Assignment
Reel/Frame 017105/0174
Security Agreement
Recorded: 2005-10-17
Received: 2005-10-20
Pages: 11
Assignor
RAMTRON INTERNATIONAL CORPORATION
Executed: 2005-10-17
Assignee
SILICON VALLEY BANK
3003 TASMAN DR., LOAN DOCUMENTATION HF154, SANTA CLARA, CA, 95054, UNITED STATES
Covered Properties
(21)
Intake Manifold Plate Adapter
Application:
11/186,848 →
Ferroelectric Non-Volatile Logic Elements
Application:
10/613,427 →
Bit-Line Shielding Method for Ferroelectric Memories
Application:
10/404,941 →
Column Decoder Configuration for a 1T/1C Memory
Application:
10/389,276 →
Ferroelectric Random Access Memory Configurable Output Driver Circuit
Application:
10/233,276 →
Method for Producing Crystallographically Textured Electrodes for Textured Pzt Capacitors
Application:
10/190,351 →
Method for Producing Crystallographically Textured Electrodes for Textured Pzt Capacitors
Application:
10/190,350 →
Capacitance Sensing Technique for Ferroelectric Random Access Memory Arrays
Application:
10/136,477 →
Ferroelectric Memory with Bit-Plate Parallel Architecture and Operating Method Thereof
Application:
10/114,535 →
Ferroelectric Non-Volatile Logic Elements
Application:
10/076,058 →
Self Referencing 1T/1C Ferroelectric Random Access Memory
Application:
10/022,119 →
Ferroelectric Random Access Memory Configurable Output Driver Circuit
Application:
09/950,560 →
Pzt Layer as a Temporary Encapsulation and Hard Mask for a Ferroelectric Capacitor
Application:
09/893,218 →
Capacitively Coupled Ferroelectric Random Access Memory Cell and a Method for Manufacturing the Same
Application:
09/873,772 →
Two Stage Low Voltage Ferroelectric Boost Circuit
Application:
09/864,851 →
Cmos Boosting Circuit Utilizing Ferroelectric Capacitors
Application:
09/864,858 →
Charge Pump or Other Charge Storage Capacitor Including Pzt Layer for Combined Use as Encapsulation Layer and Dielectric Layer of Ferroelectric Capacitor and a Method for Manufacturing the Same
Application:
09/862,365 →
Method for Manufacturing a Ferroelectric Memory Cell Including Co-Annealing
Application:
09/816,425 →
Structure for Masking Integrated Capacitors of Particular Utility for Ferroelectric Memory Integrated Circuits
Application:
09/797,394 →
Hydrogen Barrier Encapsulation Techniques for the Control of Hydrogen Induced Degradation of Ferroelectric Capacitors in Conjunction with Multilevel Metal Processing for Non-Volatile Integrated Circuit Memory Devices
Application:
09/783,496 →
Sense Amplifier Configuration for a 1T/1C Ferroelectric Memory
Application:
09/764,223 →