Patent Assignment
Reel/Frame 017606/0100
Release
Recorded: 2006-02-27
Received: 2006-03-01
Pages: 4
Assignor
SILICON VALLEY BANK
Executed: 2006-02-10
Assignee
RESHAPE, INC.
2077 GATEWAY PLACE, STE 300, SAN JOSE, CA, 95110, UNITED STATES
Covered Properties
(11)
Advanced block floorplanning in abutted hierarchical chip design
Application:
60/465,115 →
Method of Generating the Padring Layout Design Using Automation
Application:
10/264,680 →
Method of Optimizing Placement and Routing of Edge Logic in Padring Layout Design
Application:
10/264,691 →
Method of Customizing and Using Maps in Generating the Padring Layout Design
Application:
10/264,679 →
Facilitating Verification in Abutted-Pin Hierarchical Physical Design
Application:
10/104,786 →
Optimization of the Top Level in Abutted-Pin Heirarchical Physical Design
Application:
10/104,960 →
Facilitating Press Operation in Abutted-Pin Hierarchical Physical Design
Application:
10/104,813 →
Method and System for Adjusting Operating Parameters of Computer Controlled Pumps
Application:
10/041,288 →
Method and System for Maintaining Element Abstracts of an Integrated Circuit Netlist Using a Master Library File and Modifiable Master Library File
Application:
09/909,354 →
Method and System for Implementing a Graphical User Interface for Defining and Linking Multiple Attach Points for Multiple Blocks of an Integrated Circuit Netlist
Application:
09/909,050 →
Method and System for Implementing a Graphical User Interface for Depicting Loose Fly Line Interconnections Between Multiple Blocks of an Integrated Circuit Netlist
Application:
09/908,957 →