IP Library › Assignment 018746/0010

Patent Assignment

Reel/Frame 018746/0010

Termination and Release of Security Interest in Patent Rights

Recorded: 2007-01-11 Pages: 9

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Assignor

WELLS FARGO FOOTHILL, INC. (FORMERLY KNOWN AS FOOTHILL CAPITAL CORPORATION)

Executed: 2006-12-22

Assignee

INTERGRAPH CORPORATION

MAILSTOP: IW2008, HUNTSVILLE, ALABAMA, 35894

Covered Properties (36)

Video Circuit Including a Digital-to-Analog Converter in the Monitor Which Converts the Digital Data to Analog Currents Before Conversion to Analog Voltages

Patent: 4,910,685 →

Application: 06/530,607 →

Quadword Boundary Cache System

Patent: 4,860,192 →

Application: 06/915,274 →

Method and Apparatus for Addressing a Cache Memory

Patent: 4,884,197 →

Application: 06/915,319 →

Multiple Processor Accelerator for Logic Simulation

Patent: 4,873,656 →

Application: 07/067,633 →

Hardwired Pipeline Processor for Logic Simulation

Patent: 4,916,647 →

Application: 07/067,634 →

Multiple Processor Accelerator for Logic Simulation

Patent: 4,872,125 →

Application: 07/142,721 →

Method for Determining an Intuitively Defined Spatial Relationship Among Physical Entites

Patent: 4,969,114 →

Application: 07/270,255 →

Apparatus for Maintaining Consistency of a Cache Memory with a Primary Memory

Patent: 4,933,835 →

Application: 07/300,174 →

Circuit Simulation

Patent: 5,047,971 →

Application: 07/394,232 →

Cache Providing Caching /Non-Caching, Write-Through and Coptback Modes for Virtual Addresses and Including Bus Snooping to Maintain Coherency

Patent: 5,091,846 →

Application: 07/428,480 →

Apparatus and Method for Scanning by Means of a Rotatable Detector Array

Patent: 5,280,370 →

Application: 07/577,865 →

High Speed Redundant Rows and Columns for Semiconductor Memories

Patent: 5,274,593 →

Application: 07/590,243 →

Memory Address Translation System Having Modifiable and Non- Modifiable Translation Mechanisms

Patent: 5,255,384 →

Application: 07/766,906 →

System for Dynamic Segmentation Analysis Using Conversion of Relational Data into Object-Oriented Data

Patent: 5,426,780 →

Application: 07/845,337 →

A Distributed License Administration System Using a Local Policy Server to Communicate with a License Server and Control Execution of Computer Programs

Patent: 5,579,222 →

Application: 07/990,583 →

Decoder Scheme for Fully Associative Translation-Lookaside Buffer

Patent: 5,299,147 →

Application: 08/023,783 →

Pulsed Ground Circuit for Cam and Pal Memories

Patent: 5,446,685 →

Application: 08/023,904 →

3D Input System for Cad Systems

Patent: 5,461,709 →

Application: 08/024,239 →

Apparatus for Writing Data to and Reading Data from a Multi-Port Ram in a Single Clock Cycle

Patent: 5,546,569 →

Application: 08/118,378 →

Method and Apparatus for Obtaining Data from a Data Circuit Utilizing Alternating Clock Pulses to Gate the Data to the Output

Patent: 5,479,646 →

Application: 08/118,539 →

Method and Apparatus for Translating Virtual Addresses in a Data Processing System Having Multiple Instruction Pipelines and Separate Tlb's for Each Pipeline

Patent: 5,463,750 →

Application: 08/146,818 →

Apparatus for Obtaining Data from a Translation Memory Based Carry Signal from Adder

Patent: 5,502,829 →

Application: 08/148,219 →

Method and Apparatus for Enabling Control of Task Execution

Patent: 5,542,088 →

Application: 08/235,595 →

Ole for Design and Modeling

Patent: 5,682,468 →

Application: 08/378,251 →

Comparator Cell for Use in a Content Addressable Memory