Patent Assignment
Reel/Frame 018777/0202
Assignment of Assignor's Interest
Recorded: 2007-01-10
Received: 2007-01-12
Pages: 10
Assignor
AMBRIC, INC.
Executed: 2006-12-27
Assignee
SILICON VALLEY BANK
3003 TASMAN DR., LOAN DOCUMENTATION HF 154, SANTA CLARA, CA, 95054, UNITED STATES
Covered Properties
(14)
Reconfigurable Processing Array Having Hierarchical Communication Network
Application:
11/557,478 →
Reconfigurable processor array and debug network
Application:
60/850,078 →
Development System for an Integrated Circuit Having Standardized Hardware Objects
Application:
11/466,337 →
Ic Comprising Network of Microprocessors Communicating Data Messages Along Asynchronous Channel Segments Using Ports Including Validity and Accept Signal Registers and with Split/Join Capability
Application:
11/466,083 →
Leakage location method
Application:
60/836,036 →
Clock Generation for Multiple Clock Domains
Application:
11/460,231 →
System of Virtual Data Channels Across Clock Boundaries in an Integrated Circuit
Application:
11/458,061 →
MIMD computing fabric
Application:
60/790,912 →
Motion compensation in digital video
Application:
60/790,913 →
System of Virtual Data Channels in an Integrated Circuit
Application:
11/340,957 →
Asynchronous Communication Among Hardware Object Nodes in Ic with Receive and Send Ports Protocol Registers Using Temporary Register Bypass Select for Validity Information
Application:
11/326,701 →
Development System for an Integrated Circuit Having Standardized Hardware Objects
Application:
10/871,311 →
Data Interface Register Structure with Registers for Data, Validity, Group Membership Indicator, and Ready to Accept Next Member Signal
Application:
10/871,347 →
System of Hardware Objects
Application:
10/871,329 →