Patent Assignment
Reel/Frame 019047/0588
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded: 2007-03-22
Received: 2007-03-22
Pages: 6
Assignor
ADVANCED MICRO DEVICES, INC.
Executed: 2007-01-31
Assignee
SPANSION INC.
915 DEGUIGNE DRIVE, P.O. BOX 3453, MAIL STOP 250, SUNNYVALE, CA, 94088-3453, UNITED STATES
Covered Applications
(37)
MEMORY WORDLINE SPACER
App. No. 10/864,142
→
RECESSED CHANNEL
App. No. 10/683,631
→
STRUCTURE AND METHOD FOR A TWO-BIT MEMORY CELL
App. No. 10/429,140
→
METHOD FOR IMPROVING READ MARGIN IN A FLASH MEMORY DEVICE
App. No. 10/349,293
→
METHOD AND SYSTEM FOR ERASING A NITRIDE MEMORY DEVICE
App. No. 10/306,252
→
METHOD FOR FABRICATING NITRIDE MEMORY CELLS USING A FLOATING GATE FABRICATION PROCESS
App. No. 10/306,529
→
METHOD OF DETERMINING CHARGE LOSS ACTIVATION ENERGY OF A MEMORY ARRAY
App. No. 10/306,667
→
METHOD OF PROTECTING A MEMORY ARRAY FROM CHARGE DAMAGE DURING FABRICATION
App. No. 10/305,750
→
LATERAL DOPED CHANNEL
App. No. 10/305,724
→
METHOD AND SYSTEM FOR DEFINING A REDUNDANCY WINDOW AROUND A PARTICULAR COLUMN IN A MEMORY ARRAY
App. No. 10/305,700
→
SEMICONDUCTOR MANUFACTURING RESOLUTION ENHANCEMENT SYSTEM AND METHOD FOR SIMULTANEOUSLY PATTERNING DIFFERENT FEATURE TYPES
App. No. 10/283,685
→
A MULTI-BIT SILICON NITRIDE CHARGE-TRAPPING NON-VOLATILE MEMORY CELL
App. No. 10/247,641
→
REFERENCE CELL WITH VARIOUS LOAD CIRCUITS COMPENSATING FOR SOURCE SIDE LOADING EFFECTS IN A NON-VOLATILE MEMORY
App. No. 10/245,146
→
MEMORY WORDLINE SPACER
App. No. 10/243,108
→
FLOATING GATE MEMORY DEVICE WITH HOMOGENEOUS OXYNITRIDE TUNNELING DIELECTRIC
App. No. 10/232,487
→
METHOD FOR REPAIRING OVER-ERASURE OF FAST BITS IN FLOATING GATE MEMORY DEVICES
App. No. 10/215,140
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TEST STRUCTURE FOR MEASURING EFFECT OF TRENCH ISOLATION ON OXIDE IN A MEMORY DEVICE
App. No. 10/190,420
→
EXTRACTION OF DRAIN JUNCTION OVERLAP WITH THE GATE AND THE CHANNEL LENGTH FOR ULTRA-SMALL CMOS DEVICES WITH ULTRA-THIN GATE OXIDES
App. No. 10/178,144
→
METHOD FOR INCREASING CORE GAIN IN FLASH MEMORY DEVICE USING STRAINED SILICON
App. No. 10/159,323
→
BIPOLAR OR ULTRASONIC SURGICAL DEVICE
App. No. 10/128,768
→
USING A FIRST LINER LAYER AS A SPACER IN A SEMICONDUCTOR DEVICE
App. No. 10/126,207
→
PROGRAMMING WITH FLOATING SOURCE FOR LOW POWER, LOW LEAKAGE AND HIGH DENSITY FLASH MEMORY DEVICES
App. No. 10/126,330
→
NOVEL METHOD TO DISTINGUISH AN STI OUTER EDGE CURRENT COMPONENT WITH AN STI NORMAL CURRENT COMPONENT
App. No. 10/126,363
→
REPLACING A FIRST LINER LAYER WITH A THICKER OXIDE LAYER WHEN FORMING A SEMICONDUCTOR DEVICE
App. No. 10/126,841
→
METHODS AND SYSTEMS FOR FLASH MEMORY TUNNEL OXIDE RELIABILITY TESTING
App. No. 10/121,140
→
REFRESH SCHEME FOR DYNAMIC PAGE PROGRAMMING
App. No. 10/119,273
→
ALGORITHM DYNAMIC REFERENCE PROGRAMMING
App. No. 10/119,391
→
ERASE METHOD FOR A DUAL BIT MEMORY CELL
App. No. 10/119,366
→
METHOD OF DETECTING SHALLOW TRENCH ISOLATION CORNER THINNING BY ELECTRICAL TRAPPING
App. No. 10/113,259
→
METHOD OF DETECTING SHALLOW TRENCH ISOLATION CORNER THINNING BY ELECTRICAL STRESS
App. No. 10/113,152
→
MEMORY WITH DISPOSABLE ARC FOR WORDLINE FORMATION
App. No. 10/100,487
→
OVERERASE CORRECTION METHOD
App. No. 10/099,499
→
LOW COLUMN LEAKAGE FLASH MEMORY ARRAY
App. No. 10/095,739
→
FLASH MEMORY ARRAY ARCHITECTURE HAVING STAGGERED METAL LINES
App. No. 10/096,313
→
DUMMY GATE PROCESS TO REDUCE THE VSS RESISTANCE OF FLASH PRODUCTS
App. No. 10/081,246
→
PARTIAL PAGE PROGRAMMING OF MULTI LEVEL FLASH
App. No. 10/074,495
→
FLASH MEMORY ARRAY ARCHITECTURE AND METHOD OF PROGRAMMING, ERASING AND READING THEREOF
App. No. 10/013,993
→