Patent Assignment
Reel/Frame 019069/0318
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded: 2007-03-27
Received: 2007-03-27
Pages: 6
Assignor
SPANSION INC.
Executed: 2007-01-31
Assignee
SPANSION LLC
915 DEGUIGNE DRIVE, P.O. BOX 3453, MAIL STOP 250, SUNNYVALE, CA, 94088-3453, UNITED STATES
Covered Applications
(27)
HUMIDIFICATION CHAMBER WITH FLOAT-VALVE HAVING IMPROVED FLOAT
App. No. 10/446,759
→
MEMORY DEVICE
App. No. 10/413,829
→
SYSTEM AND METHOD TO FACILITATE STABILIZATION OF REFERENCE VOLTAGE SIGNALS IN MEMORY DEVICES
App. No. 10/223,486
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HIGHER PROGRAM VT AND FASTER PROGRAMMING RATES BASED ON IMPROVED ERASE METHODS
App. No. 10/173,262
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CHARGE INJECTION
App. No. 10/050,483
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NEGATIVE PUMP REGULATOR USING MOS CAPACITOR
App. No. 10/050,254
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SOURCE SIDE SENSING SCHEME FOR VIRTUAL GROUND READ OF FLASH EPROM ARRAY WITH ADJACENT BIT PRECHARGE
App. No. 10/050,257
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METHOD AND APPARATUS FOR SOFT PROGRAM VERIFICATION IN A MEMORY DEVICE
App. No. 10/050,650
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METHOD AND APPARATUS FOR PRE-CHARGING NEGATIVE PUMP MOS REGULATION CAPACITORS
App. No. 10/050,342
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DIODE FABRICATION FOR ESD/EOS PROTECTION
App. No. 10/050,394
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METHOD OF FABRICATING DOUBLE DENSED CORE GATES IN SONOS FLASH MEMORY
App. No. 09/971,483
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SALICIDED GATE FOR VIRTUAL GROUND ARRAYS
App. No. 09/968,465
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SALICIDED GATE FOR VIRTUAL GROUND ARRAYS
App. No. 09/968,456
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ESD IMPLANT FOLLOWING SPACER DEPOSITION
App. No. 09/891,885
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MODULATED CHARGE PUMP WHICH USES AN ANALOG TO DIGITAL CONVERTER TO COMPENSATE FOR SUPPLY VOLTAGE VARIATIONS
App. No. 09/892,189
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ERASE METHOD FOR DUAL BIT VIRTUAL GROUND FLASH
App. No. 09/886,861
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METHOD OF MANUFACTURING SPACER ETCH MASK FOR SILICON-OXIDE-NITRIDE-OXIDE-SILICON (SONOS) TYPE NONVOLATILE MEMORY
App. No. 09/885,490
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LOW COLUMN LEAKAGE NOR FLASH ARRAY-DOUBLE CELL IMPLEMENTATION
App. No. 09/884,565
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SPECIES IMPLANTATION FOR MINIMIZING INTERFACE DEFECT DENSITY IN FLASH MEMORY DEVICES
App. No. 09/882,242
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NOVEL RE-OXIDATION APPROACH TO IMPROVE PERIPHERAL GATE OXIDE INTEGRITY IN A TUNNEL NITRIDE OXIDATION PROCESS
App. No. 09/879,738
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METHOD AND APPARATUS FOR BOOSTING BITLINES FOR LOW VCC READ
App. No. 09/873,643
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SYSTEM AND METHOD TO FACILITATE STABILIZATION OF REFERENCE VOLTAGE SIGNALS IN MEMORY DEVICES
App. No. 09/824,166
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SINGLE BIT ARRAY EDGES
App. No. 09/795,865
→
Negative gate erase
App. No. 09/795,856
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HIGHER PROGRAM VT AND FASTER PROGRAMMING RATES BASED ON IMPROVED ERASE METHODS
App. No. 09/796,282
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Data retention characteristics as a result of high temperature bake
App. No. 09/795,849
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TAILORED ERASE METHOD USING HIGHER PROGRAM VT AND HIGHER NEGATIVE GATE ERASE
App. No. 09/795,854
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