Patent Assignment
Reel/Frame 019069/0342
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded: 2007-03-27
Received: 2007-03-27
Pages: 6
Assignor
SPANSION INC.
Executed: 2007-01-31
Assignee
SPANSION LLC
915 DEGUIGNE DRIVE, P.O. BOX 3453, MAIL STOP 250, SUNNYVALE, CA, 94088-3453, UNITED STATES
Covered Applications
(35)
MEMORY WORDLINE SPACER
App. No. 10/864,142
→
STRUCTURE AND METHOD FOR A TWO-BIT MEMORY CELL
App. No. 10/429,140
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METHOD FOR IMPROVING READ MARGIN IN A FLASH MEMORY DEVICE
App. No. 10/349,293
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METHOD AND SYSTEM FOR ERASING A NITRIDE MEMORY DEVICE
App. No. 10/306,252
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METHOD FOR FABRICATING NITRIDE MEMORY CELLS USING A FLOATING GATE FABRICATION PROCESS
App. No. 10/306,529
→
METHOD OF DETERMINING CHARGE LOSS ACTIVATION ENERGY OF A MEMORY ARRAY
App. No. 10/306,667
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METHOD OF PROTECTING A MEMORY ARRAY FROM CHARGE DAMAGE DURING FABRICATION
App. No. 10/305,750
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LATERAL DOPED CHANNEL
App. No. 10/305,724
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METHOD AND SYSTEM FOR DEFINING A REDUNDANCY WINDOW AROUND A PARTICULAR COLUMN IN A MEMORY ARRAY
App. No. 10/305,700
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SEMICONDUCTOR MANUFACTURING RESOLUTION ENHANCEMENT SYSTEM AND METHOD FOR SIMULTANEOUSLY PATTERNING DIFFERENT FEATURE TYPES
App. No. 10/283,685
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A MULTI-BIT SILICON NITRIDE CHARGE-TRAPPING NON-VOLATILE MEMORY CELL
App. No. 10/247,641
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REFERENCE CELL WITH VARIOUS LOAD CIRCUITS COMPENSATING FOR SOURCE SIDE LOADING EFFECTS IN A NON-VOLATILE MEMORY
App. No. 10/245,146
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MEMORY WORDLINE SPACER
App. No. 10/243,108
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FLOATING GATE MEMORY DEVICE WITH HOMOGENEOUS OXYNITRIDE TUNNELING DIELECTRIC
App. No. 10/232,487
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METHOD FOR REPAIRING OVER-ERASURE OF FAST BITS IN FLOATING GATE MEMORY DEVICES
App. No. 10/215,140
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TEST STRUCTURE FOR MEASURING EFFECT OF TRENCH ISOLATION ON OXIDE IN A MEMORY DEVICE
App. No. 10/190,420
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EXTRACTION OF DRAIN JUNCTION OVERLAP WITH THE GATE AND THE CHANNEL LENGTH FOR ULTRA-SMALL CMOS DEVICES WITH ULTRA-THIN GATE OXIDES
App. No. 10/178,144
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METHOD FOR INCREASING CORE GAIN IN FLASH MEMORY DEVICE USING STRAINED SILICON
App. No. 10/159,323
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USING A FIRST LINER LAYER AS A SPACER IN A SEMICONDUCTOR DEVICE
App. No. 10/126,207
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PROGRAMMING WITH FLOATING SOURCE FOR LOW POWER, LOW LEAKAGE AND HIGH DENSITY FLASH MEMORY DEVICES
App. No. 10/126,330
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NOVEL METHOD TO DISTINGUISH AN STI OUTER EDGE CURRENT COMPONENT WITH AN STI NORMAL CURRENT COMPONENT
App. No. 10/126,363
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REPLACING A FIRST LINER LAYER WITH A THICKER OXIDE LAYER WHEN FORMING A SEMICONDUCTOR DEVICE
App. No. 10/126,841
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METHODS AND SYSTEMS FOR FLASH MEMORY TUNNEL OXIDE RELIABILITY TESTING
App. No. 10/121,140
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REFRESH SCHEME FOR DYNAMIC PAGE PROGRAMMING
App. No. 10/119,273
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ALGORITHM DYNAMIC REFERENCE PROGRAMMING
App. No. 10/119,391
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ERASE METHOD FOR A DUAL BIT MEMORY CELL
App. No. 10/119,366
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METHOD OF DETECTING SHALLOW TRENCH ISOLATION CORNER THINNING BY ELECTRICAL TRAPPING
App. No. 10/113,259
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METHOD OF DETECTING SHALLOW TRENCH ISOLATION CORNER THINNING BY ELECTRICAL STRESS
App. No. 10/113,152
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MEMORY WITH DISPOSABLE ARC FOR WORDLINE FORMATION
App. No. 10/100,487
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OVERERASE CORRECTION METHOD
App. No. 10/099,499
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LOW COLUMN LEAKAGE FLASH MEMORY ARRAY
App. No. 10/095,739
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FLASH MEMORY ARRAY ARCHITECTURE HAVING STAGGERED METAL LINES
App. No. 10/096,313
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DUMMY GATE PROCESS TO REDUCE THE VSS RESISTANCE OF FLASH PRODUCTS
App. No. 10/081,246
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PARTIAL PAGE PROGRAMMING OF MULTI LEVEL FLASH
App. No. 10/074,495
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FLASH MEMORY ARRAY ARCHITECTURE AND METHOD OF PROGRAMMING, ERASING AND READING THEREOF
App. No. 10/013,993
→