Patent Assignment
Reel/Frame 019745/0859
Assignment of Assignor's Interest
Recorded: 2007-08-25
Pages: 2
Assignor
ROUH, KYOUNG BONG
Executed: 2007-06-25
Assignee
HYNIX SEMICONDUCTOR INC.
SAN 136-1, AMI-RI, BUBAL-EUB, GYEONGGI-DO, ICHEON-SI, 467-701, KOREA, REPUBLIC OF
Covered Property
(1)
Method of Fabricating a Mos Transistor Having a Gate Insulation Layer with a Lateral Portion and a Vertical Portion