IP Library Assignment 020059/0559
Patent Assignment
Reel/Frame 020059/0559

Assignment of Assignor's Interest

Recorded: 2007-10-24 Pages: 2
Assignor
NAKAHATA, HITOSHI
Executed: 2007-06-18
Assignee
OKI ELECTRIC INDUSTRY CO., LTD.
7-12, TORANOMON 1-CHOME, MINATO-KU, TOKYO, 105-8460, JAPAN
Covered Property (1)
Method of Verifying Design of Logic Circuit
Patent: 7,861,197 →
Application: 11/976,369 →
Publication: US 2008/0163144
Related Assignments (2)
Other recorded transfers of the patent in this record — the chain of ownership.
Change of Name Jan 22, 2009
From: OKI ELECTRIC INDUSTRY CO., LTD.
To: OKI SEMICONDUCTOR CO., LTD.
Reel/Frame 022162/0669 →
Change of Name Mar 21, 2014
From: OKI SEMICONDUCTOR CO., LTD
To: LAPIS SEMICONDUCTOR CO., LTD.
Reel/Frame 032495/0483 →