IP Library › Assignment 020619/0773
Patent Assignment
Reel/Frame 020619/0773

Assignment of Assignor's Interest

Recorded: 2008-03-07 Pages: 4
Assignors
MIYASHITA, HIROFUMI
Executed: 2007-10-09
KABUO, CHIE
Executed: 2007-10-09
IWAUCHI, NOBUYUKI
Executed: 2007-10-09
MATSUMURA, YOICHI
Executed: 2007-10-09
KIMURA, FUMIHIRO
Executed: 2007-10-09
GOU, TATSUO
Executed: 2007-10-09
HASHIMOTO, YUKIJI
Executed: 2007-10-09
Assignee
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
1006 OAZA KADOMA, KADOMA-SHI, OSAKA, 571-8501, JAPAN
Covered Property (1)
Interconnect Structure of Semiconductor Integrated Circuit, and Design Method and Device Therefor
Patent: 7,913,221 →
Application: 11/907,999 →
Publication: US 2008/0097641
Related Assignments (2)
Other recorded transfers of the patent in this record — the chain of ownership.
Change of Name Nov 20, 2008
From: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
To: PANASONIC CORPORATION
Reel/Frame 021897/0516 →
Assignment of Assignor's Interest May 27, 2020
From: PANASONIC CORPORATION
To: PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD.
Reel/Frame 052755/0917 →