Assignment of Assignor's Interest

Recorded: 2008-09-11 Received: 2008-09-23 Pages: 2

Assignor

SATO, TAKASHI

Executed: 2008-07-01

Assignee

FUJITSU LIMITED

1-1, KAMIKODANAKA 4-CHOME, NAKAHARA-KU, KAWASAKI-SHI, KANAGAWA 211-8588, JPX, JAPAN

Covered Properties (3)

Semiconductor Integrated Circuit and Debug Mode Determination Method

Application: 12/232,178 →

Process for Preparing Reduced Fat Frozen Potato Strips

Application: 11/053,031 →

Proportional Length Food Slicing System

Application: 10/870,701 →