IP Library Assignment 021850/0952
Patent Assignment
Reel/Frame 021850/0952

Assignment of Assignor's Interest

Recorded: 2008-11-18 Pages: 4
Assignors
HANEDA, MASAKI
Executed: 2008-09-30
SUNAYAMA, MICHIE
Executed: 2008-10-08
SHIMIZU, NORIYOSHI
Executed: 2008-10-08
OHTSUKA, NOBUYUKI
Executed: 2008-10-01
NAKAO, YOSHIYUKI
Executed: 2008-09-30
TABIRA, TAKAHIRO
Executed: 2008-09-30
Assignee
FUJITSU MICROELECTRONICS LIMITED
7-1, NISHI-SHINJUKU 2-CHOME, SHINJUKU-KU,, TOKYO, 163-0722, JAPAN
Covered Property (1)
Method of Manufacturing a Multilayer Interconnection Structure in a Semiconductor Device
Patent: 8,168,532 →
Application: 12/267,970 →
Publication: US 2009/0121355
Related Assignments (2)
Other recorded transfers of the patent in this record — the chain of ownership.
Change of Name Jul 9, 2010
From: FUJITSU MICROELECTRONICS LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 024651/0744 →
Change of Address Dec 23, 2016
From: FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 041188/0401 →