IP Library › Assignment 022973/0287

Patent Assignment

Reel/Frame 022973/0287

Assignment of Assignor's Interest

Recorded: 2009-07-18 Pages: 12

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Assignor

NEC CORPORATION

Executed: 2009-06-16

Assignee

CRESCENT MOON, LLC

4365 EXECUTIVE DRIVE, SUITE 1100, SAN DIEGO, CALIFORNIA, 92121

Covered Properties (23)

Method and Apparatus for Automatic Memory Configuration by a Computer

Patent: 5,129,069 →

Application: 07/301,607 →

Method and Apparatus for Error Detection and Localization

Patent: 5,072,450 →

Application: 07/386,340 →

High Speed Dual Port Ram Providing to the Cpu Access via a Selected Port

Patent: 5,157,776 →

Application: 07/426,489 →

Method and Apparatus for Pipelining Cache Accesses Using Anticipatory Intiation of Cache Read

Patent: 5,253,352 →

Application: 07/435,880 →

Direct Memory Acess (Dma) Request Controlling Arrangement Including Sample and Hold Circuits Capable of Handling Immediately Successive Dma Requests

Patent: 5,253,356 →

Application: 07/647,100 →

Method of Varying the Amount of Data Prefetched to a Cache Memory in Dependence on the History of Data Requests

Patent: 5,146,578 →

Application: 07/685,157 →

Computer System Which Uses a Least-Recently-Used Algorithm for Manipulating Datatags When Performing Cache Replacement

Patent: 5,224,217 →

Application: 07/924,391 →

Programmable Cache Memory Which Associates Each Section of Main Memory to Be Cached with a Status Bit Which Enables/Disables the Caching Accessibility of the Particular Section, and with the Capability of Functioning with Memory Areas of Varying Size

Patent: 5,297,270 →

Application: 08/017,972 →

Two Stage Cache Memory System and Method

Patent: 6,038,641 →

Application: 08/131,029 →

Symmetric Multiprocessing System with Unified Environment and Distributed System Functions

Patent: 6,311,286 →

Application: 08/258,752 →

Memory Controller Which Can Carry Out a High Speed Access When Supplied with Input Addresses with a Time Interval Left Between the Input Addresses Having the Same Row Address

Patent: 5,436,869 →

Application: 08/271,640 →

Image Memory Control Device

Patent: 5,530,458 →

Application: 08/281,684 →

A Multiprocessor System for Enabling Shared Access to a Memory

Patent: 6,161,162 →

Application: 08/480,047 →

Bus Control Device for Computer System Having Computer and Dma Device

Patent: 5,745,707 →

Application: 08/504,957 →

Cache Flash Controlling Method for Cache Memory System

Patent: 5,692,150 →

Application: 08/508,186 →

Rewritable Rom File Device Having Read/Write Buffer Access Control via Copy of Rewritable Area

Patent: 5,933,846 →

Application: 08/552,290 →

Protected Address Range in an Electrically Erasable Programmable Read Only Memory

Patent: 6,009,495 →

Application: 08/554,667 →

A Flash Disaster Recovery Rom and Utility to Reprogram Multiple Roms the Event of Data Corruption

Patent: 5,870,520 →

Application: 08/615,637 →

Personal Computer Interrupt Line Sharing circuit with active Interrupt Line Monitoring, And Method For Sharing A Common Interrupt Line By Active Monitoring

Patent: 6,192,425 →

Application: 08/839,626 →

Symmetric Multiprocessing System with Unified Environment and Distributed System Functions Wherein Bus Operations Related Storage Spaces Are Mapped into a Single System Address Space

Patent: 6,125,436 →

Application: 08/855,810 →

Second Level Cache Memory System

Patent: 6,256,708 →

Application: 08/919,194 →

Control System of Fifo Memories

Patent: 6,078,972 →

Application: 08/963,012 →

Memory Device Having Line Address Counter for Making Next Line Active While Current Line Is Processed

Patent: 6,215,719 →

Application: 09/468,545 →

Related Assignments (25)