Patent Assignment
Reel/Frame 023622/0558
Assignment of Assignor's Interest
Recorded: 2009-12-08
Pages: 5
Assignor
CELESTRY DESIGN SYSTEMS, INC.
Executed: 2009-12-07
Assignee
CADENCE DESIGN SYSTEMS, INC.
2655 SEELY AVE., SAN JOSE, CALIFORNIA, 95134
Covered Property
(1)
System, Ic Chip, on-Chip Test Structure, and Corresponding Method for Modeling One or More Target Interconnect Capacitances