Patent Assignment
Reel/Frame 024964/0132
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded: 2010-09-03
Received: 2010-09-03
Pages: 24
Assignor
ZILOG, INC.
Executed: 2010-02-17
Assignee
IXYS CH GMBH
MATTENSTRASSE 6, BRUEGG BEI BIEL, CHX, 2555, SWITZERLAND
Covered Applications
(64)
CLOCK INPUT FILTER CIRCUIT
App. No. 12/584,803
→
IRDA TRANSCEIVER MODULE THAT ALSO FUNCTIONS AS REMOTE CONTROL IR TRANSMITTER
App. No. 12/383,510
→
MICROCONTROLLER HAVING IN-SITU AUTOCALIBRATED INTEGRATING ANALOG-TO-DIGITAL CONVERTER (IADC)
App. No. 12/228,824
→
PROCESSING INSTRUCTION WITHOUT OPERAND BY INFERRING RELATED OPERATION AND OPERAND ADDRESS FROM PREVIOUS INSTRUCTION FOR EXTENDED PRECISION COMPUTATION
App. No. 12/228,223
→
CLOCK INPUT FILTER CIRCUIT
App. No. 12/221,783
→
GLITCH FREE CLOCK MULTIPLEXER THAT USES A DELAY ELEMENT TO DETECT A TRANSITION-FREE PERIOD IN A CLOCK SIGNAL
App. No. 12/154,057
→
CHOPPING AND OVERSAMPLING ADC HAVING REDUCED LOW FREQUENCY DRIFT
App. No. 12/148,715
→
SPREAD SPECTRUM CLOCK GENERATOR WITH CONTROLLED DELAY ELEMENTS
App. No. 12/077,282
→
FLOW CONTROL BY SUPPLYING A REMOTE START BIT ONTO A SINGLE-WIRE BUS
App. No. 11/893,333
→
MICROCONTROLLER HAVING IN-SITU AUTOCALIBRATED INTEGRATING ANALOG-TO-DIGITAL CONVERTER (IADC)
App. No. 11/601,003
→
CIRCUIT DESIGN AND OPTICS SYSTEM FOR INFRARED SIGNAL TRANSCEIVERS
App. No. 11/586,956
→
AUTO BAUD SYSTEM AND METHOD AND SINGLE PIN COMMUNICATION INTERFACE
App. No. 11/518,048
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LOW-COST LINEARITY CORRECTION IN AN ADC WITHOUT STORING LOOKUP TABLES
App. No. 11/512,295
→
CLOCK INPUT FILTER CIRCUIT
App. No. 11/495,477
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ERROR CORRECTION IN AN OVERSAMPLED ADC USING FEW STORED CALIBRATION COEFFICIENTS
App. No. 11/472,192
→
GLITCH FREE CLOCK MULTIPLEXER THAT USES A DELAY ELEMENT TO DETECT A TRANSITION-FREE PERIOD IN A CLOCK SIGNAL
App. No. 11/445,851
→
MICROCONTROLLER THAT MAINTAINS CAPACITORS OF AN ANALOG CIRCUIT IN A CHARGED STATE DURING LOW POWER OPERATION
App. No. 11/406,099
→
CHOPPING AND OVERSAMPLING ADC HAVING REDUCED LOW FREQUENCY DRIFT
App. No. 11/378,785
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MODULATING RAMP ANGLE IN A DIGITAL FREQUENCY LOCKED LOOP
App. No. 11/305,291
→
PROCESS TO IMPROVE HIGH-PERFORMANCE CAPACITORS IN INTEGRATED MOS TECHNOLOGIES
App. No. 11/289,262
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ADAPTIVE ERROR CORRECTION IN AN OVERSAMPLED ADC
App. No. 11/267,722
→
INSTRUCTION OPERATION AND OPERAND MEMORY LOCATION DETERMINED BASED ON PRECEDING INSTRUCTION OPERATION AND OPERAND MEMORY LOCATION
App. No. 11/265,421
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PROGRAMMABLE TEMPERATURE-COMPENSATED RC OSCILLATOR
App. No. 11/200,329
→
DEDICATED COMMAND PORT FOR MEMORY CONTROLLERS
App. No. 11/146,246
→
ESD PROTECTION TRANSISTOR
App. No. 11/118,680
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CALIBRATING AN ANALOG-TO-DIGITAL CONVERTER USING A TEST SIGNAL WITH A PRECISE DC VOLTAGE
App. No. 11/087,784
→
LOW-VOLTAGE BANDGAP REFERENCE CIRCUIT WITH STARTUP CONTROL
App. No. 11/081,292
→
SIGNAL RECEIVER HAVING WIDE BAND AMPLIFICATION CAPABILITY
App. No. 11/080,161
→
TEMPERATURE-COMPENSATED RC OSCILLATOR
App. No. 11/026,750
→
IRDA/RC TRASMITTER CIRCUIT HAVING LOW ENERGY CONSUMPTION
App. No. 10/996,506
→
SENDING A SCRIPT TO A VIRTUAL MACHINE FOR IMMEDIATE INTERPRETING
App. No. 10/928,502
→
LOADING A MACHINE CODE API ONTO AN 8-BIT VIRTUAL MACHINE TO ENABLE NEW FUNCTIONALITY
App. No. 10/928,830
→
INTERPRETING A COMMON SCRIPT BLOCK TO OUTPUT VARIOUS FORMS OF DATA ACCORDING TO A COMMON PROTOCOL
App. No. 10/928,501
→
BELOW-GROUND SENSOR INTERFACE AMPLIFIER
App. No. 10/928,492
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SCRIPT INSTRUCTION FOR JUMPING TO A LOCATION, INTERPRETING A PREDETERMINED NUMBER OF INSTRUCTIONS AND THEN JUMPING BACK
App. No. 10/928,014
→
IMPLEMENTING SOFTWARE BREAKPOINTS AND DEBUGGER THEREFOR
App. No. 10/913,614
→
RECOVERING ENERGY FROM AN IRDA/REMOTE CONTROL TRANSMITTER CIRCUIT
App. No. 10/897,290
→
CIRCUIT AND METHOD FOR REDUCING EAST-WEST GEOMETRY MISMATCH BETWEEN THE TOP AND BOTTOM OF A RASTER DISPLAY
App. No. 10/876,358
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SINGLE-PIN SERIAL COMMUNICATION LINK WITH START-BIT FLOW CONTROL
App. No. 10/851,460
→
FLOW CONTROL BY SUPPLYING A REMOTE START BIT ONTO A SINGLE-WIRE BUS
App. No. 10/851,882
→
ADAPTIVE ERROR CORRECTION IN AN OVERSAMPLED ADC
App. No. 10/844,901
→
ADC WITH REDUCED QUANTIZATION NOISE AND PROGRAMMABLE BIT RESOLUTION
App. No. 10/821,517
→
CIRCUIT AND METHOD FOR REDUCING EAST-WEST GEOMETRY MISMATCH BETWEEN THE TOP AND BOTTOM OF A RASTER DISPLAY
App. No. 10/820,237
→
IRDA TRANSCEIVER MODULE THAT ALSO FUNCTIONS AS REMOTE CONTROL IR TRANSMITTER
App. No. 10/788,180
→
SPREAD SPECTRUM CLOCK GENERATOR WITH CONTROLLED DELAY ELEMENTS
App. No. 10/783,338
→
Clock controller with clock source fail-safe logic
App. No. 10/764,391
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CIRCUIT FOR DETECTION OF HARDWARE FAULTS DUE TO TEMPORARY POWER SUPPLY FLUCTUATIONS
App. No. 10/750,232
→
FREQUENCY LOCKED LOOP
App. No. 10/690,874
→
ARCHITECTURE TO RELAX MEMORY PERFORMANCE REQUIREMENTS
App. No. 10/658,058
→
HARDWARE DEBUG DEVICE HAVING SCRIPT-BASED HOST INTERFACE
App. No. 10/619,644
→
COUNTING CLOCK CYCLES OVER THE DURATION OF A FIRST CHARACTER AND USING A REMAINDER VALUE TO DETERMINE WHEN TO SAMPLE A BIT OF A SECOND CHARACTER
App. No. 10/407,390
→
DIGITAL-TO-ANALOG CONVERTERS WITH REDUCED PARASITICS AND ASSOCIATED METHODS
App. No. 10/402,401
→
SELF-CALIBRATING SIGMA-DELTA ANALOG-TO-DIGITAL CONVERTER
App. No. 10/394,114
→
IMPLEMENTING SOFTWARE BREAKPOINTS
App. No. 10/356,265
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INFRARED SIGNAL COMMUNICATION SYSTEM AND METHOD INCLUDING TRANSMISSION MEANS HAVING AUTOMATIC GAIN CONTROL
App. No. 10/349,735
→
SIGMA-DELTA ANALOG-TO-DIGITAL CONVERTER WITH REDUCED QUANTIZATION NOISE
App. No. 10/331,037
→
AUTO BAUD SYSTEM AND METHOD AND SINGLE PIN COMMUNICATION INTERFACE
App. No. 10/284,600
→
SCAN VELOCITY MODULATION TECHNIQUE
App. No. 10/038,091
→
CIRCUIT AND METHOD FOR REDUCING EAST-WEST GEOMETRY MISMATCH BETWEEN THE TOP AND BOTTOM OF A RASTER DISPLAY
App. No. 10/003,824
→
CIRCUIT AND METHOD THAT ALLOWS THE AMPLITUDES OF VERTICAL CORRECTION SIGNAL COMPONENTS TO BE ADJUSTED INDEPENDENTLY
App. No. 09/981,579
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ANALOG FREQUENCY LOCKED LOOP WITH DIGITAL OVERSAMPLING FEEDBACK CONTROL AND FILTER
App. No. 09/973,979
→
APPARATUS AND METHODS FOR DEDICATED COMMAND PORT IN MEMORY CONTROLLERS
App. No. 09/971,196
→
CONTEXT SWITCHING PIPELINED MICROPROCESSOR
App. No. 09/909,507
→
ARCHITECTURE TO RELAX MEMORY PERFORMANCE REQUIREMENTS
App. No. 09/845,466
→