IP Library Assignment 025977/0842
Patent Assignment
Reel/Frame 025977/0842

Assignment of Assignor's Interest

Recorded: 2011-03-18 Pages: 2
Assignor
ISHIZU, TOMOYUKI
Executed: 2011-02-09
Assignee
PANASONIC CORPORATION
1006 OAZA KADOMA, KADOMA-SHI, OSAKA, 571-8501, JAPAN
Covered Property (1)
Semiconductor Device Layout Reducing Imbalance in Characteristics of Paired Transistors
Patent: 8,575,703 →
Application: 13/034,160 →
Publication: US 2011/0204448
Related Assignments (1)
Other recorded transfers of the patent in this record — the chain of ownership.
Assignment of Assignor's Interest May 27, 2020
From: PANASONIC CORPORATION
To: PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD.
Reel/Frame 052755/0917 →