Patent Assignment
Reel/Frame 026322/0384
Assignment of Assignor's Interest
Recorded: 2011-05-23
Pages: 9
Assignor
NASCENTRIC, INC.
Executed: 2009-10-21
Assignee
CADENCE DESIGN SYSTEMS, INC.
2655 SEELY AVENUE, BUILDING 5, SAN JOSE, CALIFORNIA, 95134
Covered Properties
(11)
Apparatus and Methods for Current-Based Models for Characterization of Electronic Circuitry
Apparatus and Methods for Interconnect Characterization in Electronic Circuitry
Apparatus and Methods for Cell Models for Timing and Power Analysis
Apparatus and Methods for Compiled Static Timing Analysis
Apparatus and Methods for Simulation of Electronic Circuitry
Apparatus and Methods for Interconnect Simulation in Electronic Circuitry Using Non-Uniform Time Step
Patent:
7,191,414 →
Application:
11/196,129 →
Replicant Simulation
Patent:
8,161,448 →
Application:
11/257,272 →
Temporal Replicant Simulation
Patent:
7,979,820 →
Application:
11/257,318 →
High Speed Memory Simulation
Patent:
8,275,597 →
Application:
12/020,871 →
Replicant Simulation
Patent:
8,069,024 →
Application:
12/165,742 →
Using Impedance (Z) Parameters to Augment Circuit Simulation
Patent:
7,970,591 →
Application:
12/169,277 →