Patent Assignment
Reel/Frame 027628/0519
Assignment of Assignor's Interest
Recorded: 2012-01-31
Pages: 3
Assignor
KAWAGOE, MASAKUNI
Executed: 2012-01-10
Assignee
LAPIS SEMICONDUCTOR CO., LTD.
550-1 HIGASHIASAKAWA-CHO HACHIOUJI-SHI, TOKYO, 193-8550, JAPAN
Covered Property
(1)
Intergrated Circuit Having Latch Circuits and Using Delay to Fetch Data Bits in Synchronization with Clock Signals
Related Assignments
(1)
Other recorded transfers of the patent in this record — the chain of ownership.