Assignment of Assignor's Interest

Recorded: 2013-05-09 Pages: 6

Assignor

Executed: 2013-04-15

Assignee

SAMSUNG ELECTRONICS CO., LTD.

416 MAETAN-DONG, YEONGTONG-GU, SUWON-SI, GYEONGGI-DO, KOREA, REPUBLIC OF

Covered Properties (5)

Dual-Pipeline Architecture for Enhancing the Performance of Grpahics Memory

Patent: 5,937,204 →

Application: 08/866,695 →

Apparatus and Method for Operating Clock Sensitive Devices in Multiple Timing Domains

Patent: 6,327,667 →

Application: 08/893,309 →

Apparatus for Spatial and Temporal Sampling in a Computer Memory System

Patent: 6,202,127 →

Application: 08/979,822 →

Large Input Function Replaying Dynamic Entry Latch with Static and Monotonic Dual Rail Outputs

Patent: 6,388,489 →

Application: 09/449,796 →

Method and Circuits for Early Detection of a Full Queue

Patent: 8,090,930 →

Application: 10/356,943 →

Publication: US 2003/0120898

Related Assignments (2)

Other recorded transfers of the patents in this record — the chain of ownership.