Patent Assignment
Reel/Frame 030405/0435
Assignment of Assignor's Interest
Recorded: 2013-05-13
Pages: 4
Assignors
YANG, HARN-BOR
Executed: 2013-05-06
CHEN, CHIA-CHENG
Executed: 2013-05-06
WU, CHING-WEI
Executed: 2013-05-06
Assignee
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
NO. 8, LI-HSIN ROAD 6, HSIN-CHU SCIENCE PARK, HSIN-CHU, 300-77, TAIWAN
Covered Property
(1)
Timing Logic for Memory Array