IP Library › Assignment 030665/0729
Patent Assignment
Reel/Frame 030665/0729

Assignment of Assignor's Interest

Recorded: 2013-06-21 Pages: 4
Assignors
PATEL, SANTOSH
Executed: 2013-06-17
ANANTULA, PRADEEP
Executed: 2013-06-17
Assignee
CONEXANT SYSTEMS, INC.
1901 MAIN STREET, SUITE 300, IRVINE, CALIFORNIA, 92614
Covered Property (1)
Low Area All Digital Delay-Locked Loop Insensitive to Reference Clock Duty Cycle and Jitter
Patent: 8,779,816 →
Application: 13/919,973 →
Publication: US 2013/0342251
Related Assignments (4)
Other recorded transfers of the patent in this record — the chain of ownership.
Release of Security Interest May 6, 2016
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
To: CONEXANT SYSTEMS, INC.; CONEXANT, INC.; CONEXANT SYSTEMS WORLDWIDE, INC.; BROOKTREE BROADBAND HOLDING, INC.
Reel/Frame 038631/0452 →
Change of Name Jun 26, 2017
From: CONEXANT SYSTEMS, INC.
To: CONEXANT SYSTEMS, LLC
Reel/Frame 042986/0613 →
Assignment of Assignor's Interest Sep 7, 2017
From: CONEXANT SYSTEMS, LLC
To: SYNAPTICS INCORPORATED
Reel/Frame 043786/0267 →
Security Interest Sep 27, 2017
From: SYNAPTICS INCORPORATED
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 044037/0896 →