IP Library Assignment 032081/0749
Patent Assignment
Reel/Frame 032081/0749

Assignment of Assignor's Interest

Recorded: 2013-12-20 Pages: 3
Assignor
KAWAMURA, TAKU
Executed: 2013-12-05
Assignee
FUJITSU SEMICONDUCTOR LIMITED
2-10-23 SHIN-YOKOHAMA, KOHOKU-KU, YOKOHAMA-SHI, KANAGAWA 222-0033, JAPAN
Covered Property (1)
Method and Apparatus for Verifying Circuit Design
Patent: 9,547,568 →
Application: 14/134,435 →
Publication: US 2014/0214355
Related Assignments (1)
Other recorded transfers of the patent in this record — the chain of ownership.
Assignment of Assignor's Interest Apr 23, 2015
From: FUJITSU SEMICONDUCTOR LIMITED
To: SOCIONEXT INC.
Reel/Frame 035481/0236 →