Patent Assignment
Reel/Frame 032487/0978
Assignment of Assignor's Interest
Recorded: 2014-03-20
Pages: 2
Assignors
CHUANG, YI-LIN
Executed: 2014-03-07
CHEN, CHING-FANG
Executed: 2014-03-07
SHEN, JIA-JYE
Executed: 2014-03-07
Assignee
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
NO. 8, LI-HSIN RD. VI, HSINCHU SCIENCE PARK, HSINCHU, 300, TAIWAN
Covered Property
(1)
Method for Layout Design and Structure with Inter-Layer Vias