IP Library Assignment 033147/0830
Patent Assignment
Reel/Frame 033147/0830

Assignment of Assignor's Interest

Recorded: 2014-06-20 Pages: 7
Assignors
CHANG, YU-HSING
Executed: 2014-06-19
WU, CHANG-MING
Executed: 2014-06-19
LIU, SHIH-CHANG
Executed: 2014-06-19
Assignee
TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
NO. 8, LI-HSIN RD. 6, HSIN-CHU SCIENCE PARK, HSIN-CHU, 300-77, TAIWAN
Covered Property (1)
Pattern Layout to Prevent Split Gate Flash Memory Cell Failure
Patent: 9,356,142 →
Application: 14/310,277 →
Publication: US 2015/0372136