IP Library Assignment 033906/0508
Patent Assignment
Reel/Frame 033906/0508

Assignment of Assignor's Interest

Recorded: 2014-10-07 Pages: 4
Assignor
POLEDNA, STEFAN
Executed: 2014-08-28
Assignee
FTS COMPUTERTECHNIK GMBH
SCHÖNBRUNNER STRASSE 7, WIEN, A-1040, AUSTRIA
Covered Property (1)
Method and Master Clock for Generating Fail-Silent Synchronization Messages
Patent: 9,130,661 →
Application: 14/391,161 →
Publication: US 2015/0098492
Related Assignments (1)
Other recorded transfers of the patent in this record — the chain of ownership.
Merger Sep 14, 2018
From: FTS COMPUTERTECHNIK GMBH
To: TTTECH COMPUTERTECHNIK AG
Reel/Frame 047648/0566 →