Patent Assignment
Reel/Frame 034689/0296
CORRECTIVE ASSIGNMENT TO ENCLUDE THE SCHEDULES FULL LIST. PREVIOUSLY RECORDED ON RELL 019069 FRAME 0318. ASSIGNOR(S) HEREBY CONFIRMS THE SCHEDULE.
Recorded: 2014-12-22
Received: 2014-12-22
Pages: 36
Assignor
SPANSION INC.
Executed: 2007-01-31
Assignee
SPANSION LLC
915 DEGUIGNE DRIVE, P.O. BOX 3453, MAIL STOP 250, SUNNYVALE, CA, 94088-3453, UNITED STATES
Covered Applications
(27)
5 RINGER EQUIVALENT NUMBER (REN) RINGER CIRCUIT USING A HIGH VOLTAGE LEVEL TRANSLATOR AND A SOURCE FOLLOWER BUFFER AND METHOD THEREFOR
App. No. 12/724,298
→
LED DRIVER WITH LOW HARMONIC DISTORTION OF INPUT AC CURRENT AND METHODS OF CONTROLLING THE SAME
App. No. 12/269,512
→
MEMORY DEVICE
App. No. 10/413,829
→
SYSTEM AND METHOD TO FACILITATE STABILIZATION OF REFERENCE VOLTAGE SIGNALS IN MEMORY DEVICES
App. No. 10/223,486
→
HIGHER PROGRAM VT AND FASTER PROGRAMMING RATES BASED ON IMPROVED ERASE METHODS
App. No. 10/173,262
→
CHARGE INJECTION
App. No. 10/050,483
→
NEGATIVE PUMP REGULATOR USING MOS CAPACITOR
App. No. 10/050,254
→
SOURCE SIDE SENSING SCHEME FOR VIRTUAL GROUND READ OF FLASH EPROM ARRAY WITH ADJACENT BIT PRECHARGE
App. No. 10/050,257
→
METHOD AND APPARATUS FOR SOFT PROGRAM VERIFICATION IN A MEMORY DEVICE
App. No. 10/050,650
→
METHOD AND APPARATUS FOR PRE-CHARGING NEGATIVE PUMP MOS REGULATION CAPACITORS
App. No. 10/050,342
→
DIODE FABRICATION FOR ESD/EOS PROTECTION
App. No. 10/050,394
→
METHOD OF FABRICATING DOUBLE DENSED CORE GATES IN SONOS FLASH MEMORY
App. No. 09/971,483
→
SALICIDED GATE FOR VIRTUAL GROUND ARRAYS
App. No. 09/968,465
→
SALICIDED GATE FOR VIRTUAL GROUND ARRAYS
App. No. 09/968,456
→
ESD IMPLANT FOLLOWING SPACER DEPOSITION
App. No. 09/891,885
→
MODULATED CHARGE PUMP WHICH USES AN ANALOG TO DIGITAL CONVERTER TO COMPENSATE FOR SUPPLY VOLTAGE VARIATIONS
App. No. 09/892,189
→
ERASE METHOD FOR DUAL BIT VIRTUAL GROUND FLASH
App. No. 09/886,861
→
METHOD OF MANUFACTURING SPACER ETCH MASK FOR SILICON-OXIDE-NITRIDE-OXIDE-SILICON (SONOS) TYPE NONVOLATILE MEMORY
App. No. 09/885,490
→
LOW COLUMN LEAKAGE NOR FLASH ARRAY-DOUBLE CELL IMPLEMENTATION
App. No. 09/884,565
→
NOVEL RE-OXIDATION APPROACH TO IMPROVE PERIPHERAL GATE OXIDE INTEGRITY IN A TUNNEL NITRIDE OXIDATION PROCESS
App. No. 09/879,738
→
METHOD AND APPARATUS FOR BOOSTING BITLINES FOR LOW VCC READ
App. No. 09/873,643
→
SYSTEM AND METHOD TO FACILITATE STABILIZATION OF REFERENCE VOLTAGE SIGNALS IN MEMORY DEVICES
App. No. 09/824,166
→
SINGLE BIT ARRAY EDGES
App. No. 09/795,865
→
Negative gate erase
App. No. 09/795,856
→
HIGHER PROGRAM VT AND FASTER PROGRAMMING RATES BASED ON IMPROVED ERASE METHODS
App. No. 09/796,282
→
Data retention characteristics as a result of high temperature bake
App. No. 09/795,849
→
TAILORED ERASE METHOD USING HIGHER PROGRAM VT AND HIGHER NEGATIVE GATE ERASE
App. No. 09/795,854
→