Patent Assignment
Reel/Frame 035902/0641
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded: 2015-06-12
Received: 2015-06-12
Pages: 152
Assignor
SPANSION LLC
Executed: 2015-06-01
Assignee
CYPRESS SEMICONDUCTOR CORPORATION
198 CHAMPION COURT, SAN JOSE, CA, 95134, UNITED STATES
Covered Applications
(20)
Analog-Digital Conversion System and Method for Controlling the Same
App. No. 14/503,585
→
NON-VOLATILE MEMORY WITH SILICIDED BIT LINE CONTACTS
App. No. 14/501,536
→
Method to Improve Charge Trap Flash Memory Core Cell Performance and Reliability
App. No. 14/486,421
→
SWITCHING CIRCUIT
App. No. 14/464,783
→
METAL-INSUALTOR-METAL (MIM) DEVICE AND METHOD OF FORMATION THEREROF
App. No. 14/460,205
→
INTEGRATION OF SEMICONDUCTOR MEMORY CELLS AND LOGIC CELLS
App. No. 14/458,542
→
HOST/CLIENT SYSTEM HAVING A SCALABLE SERIAL BUS INTERFACE
App. No. 14/453,306
→
SPLIT-GATE SEMICONDUCTOR DEVICE WITH L-SHAPED GATE
App. No. 14/450,727
→
CONTROL APPARATUS, AND CONTROL METHOD FOR BUCK-BOOST POWER SUPPLY WITH TWO PRIMARY SWITCHES
App. No. 14/447,688
→
CONTROL APPARATUS, SWITCHING POWER SUPPLY AND CONTROL METHOD FOR MAINTAINING POWER CONVERSION EFFICIENCY
App. No. 14/448,442
→
CRYSTAL OSCILLATION CIRCUIT
App. No. 14/446,678
→
DETECTING THE DRIFT OF THE DATA VALID WINDOW IN A TRANSACTION
App. No. 14/339,377
→
CONTROL CIRCUIT AND CONTROL METHOD FOR DIMMING A LIGHTING DEVICE
App. No. 14/315,713
→
Inter-Bus Communication Interface Device
App. No. 14/297,200
→
TILTED IMPLANT FOR POLY RESISTORS
App. No. 14/278,114
→
METHOD TO IMPROVE CHARGE TRAP FLASH MEMORY TOP OXIDE QUALITY
App. No. 14/270,700
→
MITIGATE FLASH WRITE LATENCY AND BANDWIDTH LIMITATION BY PREFERENTIALLY STORING FREQUENTLY WRITTEN SECTORS IN CACHE MEMORY DURING A DATABURST
App. No. 14/269,299
→
DATA PATTERN ANALYSIS
App. No. 14/258,076
→
OPERATING SYSTEM BASED DRAM AND FLASH MANAGEMENT
App. No. 14/253,056
→
MEMORY BUFFERING SYSTEM THAT IMPROVES READ/WRITE PERFORMANCE AND PROVIDES LOW LATENCY FOR MOBILE SYSTEMS
App. No. 14/250,113
→