Patent Assignment
Reel/Frame 036032/0333
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded: 2015-06-29
Received: 2015-06-29
Pages: 153
Assignor
SPANSION, LLC
Executed: 2015-06-01
Assignee
CYPRESS SEMICONDUCTOR CORPORATION
198 CHAMPION COURT, SAN JOSE, CA, 95134, UNITED STATES
Covered Applications
(46)
TRENCH SIDE WALL CHARGE TRAPPING DIELECTRIC FLASH MEMORY DEVICE
App. No. 10/430,582
→
PROCESS FOR REDUCING HYDROGEN CONTAMINATION IN DIELECTRIC MATERIALS IN MEMORY DEVICES
App. No. 10/429,447
→
DIFFERENTIAL CIRCUIT AND PEAK HOLD CIRCUIT INCLUDING DIFFERENTIAL CIRCUIT
App. No. 10/418,197
→
CIRCUIT FOR FAST AND ACCURATE MEMORY READ OPERATIONS
App. No. 10/387,617
→
MEMORY ARRAY HAVING SHALLOW BIT LINE WITH SILICIDE CONTACT PORTION AND METHOD OF FORMATION
App. No. 10/382,731
→
PERFORMANCE IN FLASH MEMORY DEVICES
App. No. 10/358,866
→
METHOD OF IMPROVING DYNAMIC REFERENCE TRACKING FOR FLASH MEMORY UNIT
App. No. 10/357,879
→
MEMORY CIRCUIT ARRANGEMENT FOR PROGRAMMING A MEMORY CELL
App. No. 10/348,732
→
SYSTEM AND METHOD FOR CHARGE RESTORATION IN A NON-VOLATILE MEMORY DEVICE
App. No. 10/338,333
→
FLASH MEMORY DEVICE HAVING FOUR-BIT CELLS
App. No. 10/315,632
→
CIRCUIT FOR ACCURATE MEMORY READ OPERATIONS
App. No. 10/313,444
→
METHOD OF FORMING COPPER SULFIDE FOR MEMORY CELL
App. No. 10/314,060
→
EFFICIENT METHOD TO DETECT PROCESS INDUCED DEFECTS IN THE GATE STACK OF FLASH MEMORY DEVICES
App. No. 10/313,676
→
STRUCTURE AND METHOD FOR REDUCING CHARGE LOSS IN A MEMORY CELL
App. No. 10/313,454
→
METHOD FOR FABRICATING NITRIDE MEMORY CELLS USING A FLOATING GATE FABRICATION PROCESS
App. No. 10/306,529
→
PROGRAM ALGORITHM INCLUDING SOFT ERASE FOR SONOS MEMORY DEVICE
App. No. 10/305,756
→
METHOD OF FORMING FLASH MEMORY HAVING PRE-INTERPOLY DIELECTRIC TREATMENT LAYER
App. No. 10/291,293
→
MEMORY CELL FORMATION WITH PROCESS FOR PATTERNING CONDUCTING POLYMER FILMS
App. No. 10/285,183
→
METHOD OF PROGRAMMING IN-SERIES MEMORY CELLS
App. No. 10/282,847
→
REFERENCE CELL WITH VARIOUS LOAD CIRCUITS COMPENSATING FOR SOURCE SIDE LOADING EFFECTS IN A NON-VOLATILE MEMORY
App. No. 10/245,146
→
METHOD AND SYSTEM TO MINIMIZE PAGE PROGRAMMING TIME FOR FLASH MEMORY DEVICES
App. No. 10/243,792
→
PATH GATE DRIVER CIRCUIT
App. No. 10/243,433
→
FLASH MEMORY ARRAY WITH DUAL FUNCTION CONTROL LINES AND ASYMMETRICAL SOURCE AND DRAIN JUNCTIONS
App. No. 10/233,906
→
MEMORY DEVICE AND METHOD OF MAKING
App. No. 10/223,920
→
METHOD OF DETERMINING THE ACTIVE REGION WIDTH BETWEEN SHALLOW TRENCH ISOLATION STRUCTURES USING A GATE CURRENT MEASUREMENT TECHNIQUE FOR FABRICATING A FLASH MEMORY SEMICONDUCTOR DEVICE AND DEVICE THEREBY FORMED
App. No. 10/224,737
→
SALICIDED GATE FOR VIRTUAL GROUND ARRAYS
App. No. 10/217,821
→
NONVOLATILE MEMORY CELL WITH A NITRIDATED OXIDE LAYER
App. No. 10/199,793
→
HIGH DENSITY DUAL BIT FLASH MEMORY CELL WITH NON PLANAR STRUCTURE
App. No. 10/164,895
→
METHOD OF DRIVING A SEMICONDUCTOR MEMORY
App. No. 10/160,050
→
SEMICONDUCTOR ISOLATION MATERIAL DEPOSITION SYSTEM AND METHOD
App. No. 10/159,078
→
USING A FIRST LINER LAYER AS A SPACER IN A SEMICONDUCTOR DEVICE
App. No. 10/126,207
→
MEMORY MANUFACTURING PROCESS USING DISPOSABLE ARC FOR WORDLINE FORMATION
App. No. 10/126,280
→
PRECISION HIGH-K INTERGATE DIELECTRIC LAYER
App. No. 10/117,818
→
STACKED POLYSILICON LAYER FOR BORON PENETRATION INHIBITION
App. No. 10/118,363
→
METHOD OF DETERMINING LOCATION OF GATE OXIDE BREAKDOWN OF MOSFET BY MEASURING CURRENTS
App. No. 10/113,017
→
METHOD OF DETECTING SHALLOW TRENCH ISOLATION CORNER THINNING BY ELECTRICAL STRESS
App. No. 10/113,152
→
MEMORY ARRAY WITH BURIED BIT LINES
App. No. 10/095,512
→
PASSWORD AND DYNAMIC PROTECTION OF FLASH MEMORY DATA
App. No. 10/091,767
→
SEMICONDUCTOR MEMORY AND METHOD OF MANUFACTURE THEREOF
App. No. 10/085,023
→
NROM CELL WITH N-LESS CHANNEL
App. No. 10/086,112
→
DC-DC CONVERTER WITH CONTROL CIRCUIT CAPABLE OF GENERATING STEP-UP AND STEP-DOWN SIGNALS
App. No. 10/083,592
→
PLANAR TRANSISTOR STRUCTURE USING ISOLATION IMPLANTS FOR IMPROVED VSS RESISTANCE AND FOR PROCESS SIMPLIFICATION
App. No. 10/032,646
→
METHOD FOR MANUFACTURING MEMORY WITH HIGH CONDUCTIVITY BITLINE AND SHALLOW TRENCH ISOLATION INTEGRATION
App. No. 10/022,292
→
METHOD OF DETERMINING GATE OXIDE THICKNESS OF AN OPERATIONAL MOSFET
App. No. 10/017,832
→
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE WITH VARIABLE GAIN AMPLIFIER
App. No. 09/972,152
→
METHOD AND SYSTEM FOR DECREASING THE SPACES BETWEEN WORDLINES
App. No. 09/777,457
→