Patent Assignment
Reel/Frame 036034/0058
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded: 2015-06-29
Received: 2015-06-29
Pages: 153
Assignor
SPANSION, LLC
Executed: 2015-06-01
Assignee
CYPRESS SEMICONDUCTOR CORPORATION
198 CHAMPION COURT, SAN JOSE, CA, 95134, UNITED STATES
Covered Applications
(25)
METHOD FOR FABRICATING SELF-ALIGNED GATE OF FLASH MEMORY CELL
App. No. 10/150,556
→
METHOD FOR FORMING A SEMICONDUCTOR DEVICE WITH SELF-ALIGNED CONTACTS USING A LINER OXIDE LAYER
App. No. 10/109,526
→
METHOD OF MAKING MEMORY WORDLINE HARD MASK EXTENSION
App. No. 10/109,516
→
DUMMY GATE PROCESS TO REDUCE THE VSS RESISTANCE OF FLASH PRODUCTS
App. No. 10/081,246
→
NONVOLATILE SEMICONDUCTOR MEMORY
App. No. 10/043,114
→
METHOD FOR REPAIRING DAMAGE TO CHARGE TRAPPING DIELECTRIC LAYER FROM BIT LINE IMPLANTATION
App. No. 10/023,349
→
FLASH MEMORY DEVICE WITH INCREASE OF EFFICIENCY DURING AN APDE (AUTOMATIC PROGRAM DISTURB AFTER ERASE) PROCESS
App. No. 09/969,572
→
NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND FABRICATION PROCESS THEREOF
App. No. 09/963,632
→
METHOD AND SYSTEM FOR ETCHING TUNNEL OXIDE TO REDUCE UNDERCUTTING DURING MEMORY ARRAY FABRICATION
App. No. 09/925,205
→
DETERMINATION OF DIELECTRIC CONSTANTS OF THIN DIELECTRIC MATERIALS IN A MOS (METAL OXIDE SEMICONDUCTOR) STACK
App. No. 09/904,736
→
METHOD OF PROGRAMMING A NON-VOLATILE MEMORY CELL USING A VERTICAL ELECTRIC FIELD
App. No. 09/899,721
→
METHOD OF MANUFACTURING SPACER ETCH MASK FOR SILICON-OXIDE-NITRIDE-OXIDE-SILICON (SONOS) TYPE NONVOLATILE MEMORY
App. No. 09/885,490
→
METHOD OF PROGRAMMING A NON-VOLATILE MEMORY CELL USING A DRAIN BIAS
App. No. 09/880,367
→
SHARED MEMORY APPARATUS AND METHOD FOR MULTIPROCESSOR SYSTEMS
App. No. 09/859,193
→
SOFT PROGRAM AND SOFT PROGRAM VERIFY OF THE CORE CELLS IN FLASH MEMORY ARRAY
App. No. 09/829,193
→
SYSTEM AND METHOD TO FACILITATE STABILIZATION OF REFERENCE VOLTAGE SIGNALS IN MEMORY DEVICES
App. No. 09/824,166
→
SEMICONDUCTOR MEMORY DEVICE HAVING SOURCE AREAS OF MEMORY CELLS SUPPLIED WITH A COMMON VOLTAGE
App. No. 09/818,652
→
TRIMMING CIRCUIT OF SEMICONDUCTOR APPARATUS
App. No. 09/816,749
→
ACTIVE LOAD CIRCUIT, AND OPERATIONAL AMPLIFIER AND COMPARATOR HAVING THE SAME
App. No. 09/796,549
→
SINGLE BIT ARRAY EDGES
App. No. 09/795,865
→
METHOD OF FORMING A VOID-FREE INTERLAYER DIELECTRIC (ILD0) FOR 0.18-UM FLASH MEMORY TECHNOLOGY AND SEMICONDUCTOR DEVICE THEREBY FORMED
App. No. 09/788,045
→
SERVO CONTROLLER AND SERVO CONTROL METHOD
App. No. 09/782,297
→
CONCURRENT PROGRAM RECONNAISSANCE WITH PIGGYBACK PULSES FOR MULTI-LEVEL CELL FLASH MEMORY DESIGNS
App. No. 09/779,764
→
PIGGYBACK PROGRAMMING USING TIMING CONTROL FOR MULTI-LEVEL CELL FLASH MEMORY DESIGNS
App. No. 09/779,792
→
THREE METAL PROCESS FOR OPTIMIZING LAYOUT DENSITY
App. No. 09/767,341
→