Patent Assignment
Reel/Frame 036042/0390
CHANGE OF NAME
Recorded: 2015-07-01
Received: 2015-07-01
Pages: 7
Assignor
STEC, INC.
Executed: 2013-11-05
Assignee
HGST TECHNOLOGIES SANTA ANA, INC.
3001 DAIMLER STREET, SANTA ANA, CA, 92705, UNITED STATES
Covered Applications
(100)
SETTING OPERATING PARAMETERS FOR MEMORY CELLS BASED ON WORDLINE ADDRESS AND CYCLE INFORMATION
App. No. 14/724,773
→
HIGH SPEED INPUT/OUTPUT PERFORMANCE IN SOLID STATE DEVICES
App. No. 14/720,697
→
WORD-LINE INTER-CELL INTERFERENCE DETECTOR IN FLASH SYSTEM
App. No. 14/313,971
→
FLASH STORAGE DEVICE WITH READ DISTURB MITIGATION
App. No. 14/257,978
→
APPARATUS AND METHOD FOR DETERMINING AN OPERATING CONDITION OF A MEMORY CELL BASED ON CYCLE INFORMATION
App. No. 14/252,746
→
SYSTEM AND METHOD FOR STORING DATA USING A FLEXIBLE DATA FORMAT
App. No. 13/925,789
→
OFFLINE AWAY MESSAGES
App. No. 13/899,895
→
READ LEVEL ADJUSTMENT USING SOFT INFORMATION
App. No. 13/899,447
→
SYSTEM AND METHOD FOR ACCESSING AND STORING INTERLEAVED DATA
App. No. 13/873,183
→
SYSTEMS AND METHODS OF USING DYNAMIC DATA FOR WEAR LEVELING IN SOLID-STATE DEVICES
App. No. 13/853,989
→
SYSTEM AND METHOD FOR SCANNING FLASH MEMORIES
App. No. 13/843,218
→
POWER ARBITRATION FOR STORAGE DEVICES
App. No. 13/842,101
→
SOFT INFORMATION MODULE
App. No. 13/843,225
→
DETERMINING BIAS INFORMATION FOR OFFSETTING OPERATING VARIATIONS IN MEMORY CELLS BASED ON WORDLINE ADDRESS
App. No. 13/776,590
→
ADJUSTING OPERATING PARAMETERS FOR MEMORY CELLS BASED ON WORDLINE ADDRESS AND CYCLE INFORMATION
App. No. 13/775,070
→
REDUCED COMPLEXITY NON-BINARY LDPC DECODING ALGORITHM
App. No. 13/764,649
→
DATA STORAGE SYSTEM WITH PRIMARY AND SECONDARY COMPRESSION ENGINES
App. No. 13/754,837
→
PROGRAMMING ALGORITHM FOR IMPROVED FLASH MEMORY ENDURANCE AND RETENTION
App. No. 13/741,119
→
ERASE-SUSPEND SYSTEM AND METHOD
App. No. 13/733,835
→
SYSTEM AND METHOD FOR REDUCING MEMORY IN A MULTI-CHANNEL PARALLEL ENCODER SYSTEM
App. No. 13/728,944
→
WORD-LINE INTER-CELL INTERFERENCE DETECTOR IN FLASH SYSTEM
App. No. 13/725,689
→
INTER-CELL INTERFERENCE ALGORITHMS FOR SOFT DECODING OF LDPC CODES
App. No. 13/725,943
→
SYSTEM AND METHOD FOR STREAMING DATA IN FLASH MEMORY APPLICATIONS
App. No. 13/723,111
→
APPARATUS FOR STACKING INTEGRATED CIRCUITS
App. No. 13/720,849
→
SYSTEM AND METHOD FOR STORING DATA USING A FLEXIBLE DATA FORMAT
App. No. 13/719,184
→
DYNAMIC LDPC CODE RATE SOLUTION
App. No. 13/678,416
→
OPTIMIZED GARBAGE COLLECTION ALGORITHM TO IMPROVE SOLID STATE DRIVE RELIABILITY
App. No. 13/664,335
→
WEAR LEVELING IN SOLID-STATE DEVICE
App. No. 13/597,158
→
FLASH STORAGE SYSTEM AND METHOD FOR ACCESSING A BOOT PROGRAM
App. No. 13/590,123
→
ERROR INDICATOR FROM ECC DECODER
App. No. 13/584,698
→
BACKEND ORGANIZATION OF STORED DATA
App. No. 13/559,535
→
MANAGING SECURITY IN SOLID-STATE DEVICES
App. No. 13/555,052
→
SECURE MEMORY DEVICES AND METHODS OF MANAGING SECURE MEMORY DEVICES
App. No. 13/555,050
→
OPTIMAL PROGRAMMING LEVELS FOR LDPC
App. No. 13/553,707
→
SYSTEM AND METHOD OF USING STRIPES FOR RECOVERING DATA IN A FLASH STORAGE SYSTEM
App. No. 13/532,718
→
FLASH STORAGE DEVICE WITH DATA INTEGRITY PROTECTION
App. No. 13/530,026
→
REDUCED MEMORY MULTI-CHANNEL PARALLEL ENCODER SYSTEM
App. No. 13/526,446
→
HIGH SPEED HARD LDPC DECODER
App. No. 13/525,009
→
READ LEVEL ADJUSTMENT USING SOFT INFORMATION
App. No. 61/650,419
→
SOFT INFORMATION MODULE
App. No. 61/639,040
→
SYSTEM AND METHOD FOR SCANNING FLASH MEMORIES
App. No. 61/614,454
→
POWER ARBITRATION
App. No. 61/613,916
→
FLASH MEMORY WORDLINE VARIATION COMPENSATION
App. No. 61/602,552
→
REDUCED COMPLEXITY NON-BINARY LDPC DECODING ALGORITHM
App. No. 61/597,690
→
ERASE-SUSPEND SYSTEM AND METHOD
App. No. 13/365,232
→
PROGRAMMING ALGORITHM FOR IMPROVED FLASH MEMORY ENDURANCE AND RETENTION
App. No. 61/586,652
→
LOW DENSITY PARITY CHECK CODE DECODING SYSTEM AND METHOD
App. No. 13/343,684
→
STREAMING PROTOCOL FOR SSD APPLICATION
App. No. 61/580,113
→
WORD-LINE INTER-CELL INTERFERENCE DETECTOR IN FLASH SYSTEM
App. No. 61/580,140
→
INTER-CELL INTERFERENCE ALGORITHMS FOR SOFT DECODING OF LDPC CODES
App. No. 61/580,142
→
FLEXIBLE CODE RATE LDPC SOLUTION
App. No. 61/560,762
→
INTERLEAVED FLASH STORAGE SYSTEM AND METHOD
App. No. 13/289,966
→
LDPC DECODING FOR SOLID STATE STORAGE DEVICES
App. No. 13/277,876
→
ASYMMETRIC LOG-LIKELIHOOD RATIO FOR MLC FLASH CHANNEL
App. No. 13/253,029
→
OPTIMAL PROGRAMMING LEVELS FOR LDPC
App. No. 61/525,437
→
HIGH SPEED HARD LDPC DECODER
App. No. 61/525,705
→
ERROR INDICATOR FROM ECC DECODER
App. No. 61/525,430
→
BACKEND MAPPED ECC
App. No. 61/513,486
→
MULTI-RATE LDPC SOLUTIONS
App. No. 61/513,480
→
METHOD AND APPARATUS FOR REDUCED MEMORY MULTI-CHANNEL LDPC ENCODER/DECODER SYSTEM
App. No. 61/513,485
→
APPARATUS AND METHOD FOR DETERMINING A READ LEVEL OF A FLASH MEMORY AFTER AN INACTIVE PERIOD OF TIME
App. No. 13/179,466
→
APPARATUS AND METHOD FOR DETERMINING AN OPERATING CONDITION OF A MEMORY CELL BASED ON CYCLE INFORMATION
App. No. 13/177,518
→
APPARATUS AND METHOD FOR MULTI-MODE OPERATION OF A FLASH MEMORY DEVICE
App. No. 13/177,482
→
SYSTEM AND METHOD FOR DETERMINING DATA DEPENDENT NOISE CALCULATION FOR A FLASH CHANNEL
App. No. 13/176,727
→
TRELLIS-CODED MODULATION IN A MULTI-LEVEL CELL FLASH MEMORY DEVICE
App. No. 13/118,137
→
APPARATUS AND METHOD FOR DETERMINING A READ LEVEL OF A MEMORY CELL BASED ON CYCLE INFORMATION
App. No. 13/076,340
→
APPARATUS AND METHOD FOR DETERMINING AN OPERATING CONDITION OF A MEMORY CELL BASED ON CYCLE INFORMATION
App. No. 13/044,464
→
ERASE-SUSPEND APPARATUS AND PROCESS FOR IMPROVING SSD PERFORMANCE AND REDUCING FLASH WEAR-OUT
App. No. 61/439,296
→
LDPC DECODING FOR SOLID STATE DRIVES
App. No. 61/405,156
→
ASYMMETRIC LOG-LIKELIHOOD RATIO FOR MLC READ
App. No. 61/390,100
→
DATA STORAGE SYSTEM WITH COMPRESSION/DECOMPRESSION
App. No. 12/842,919
→
SOLID STATE STORAGE DEVICE WITH REMOVABLE POWER BACKUP
App. No. 12/842,930
→
SOLID-STATE STORAGE DEVICE WITH MULTI-LEVEL ADDRESSING
App. No. 12/842,950
→
SSD READ LEVEL PREDICTION AND ESTIMATION AND READ RETRY ALGORITHM TO DETERMINE BEST READ OPERATING CONDITIONS
App. No. 61/363,157
→
ENDURANCE DRIVEN CAPACITY MANAGEMENT FOR FLASH MEMORY
App. No. 61/362,263
→
RUN-TIME DYNAMIC PROGRAM/ERASE ALGORITHM TO DETERMINE THE BEST OPERATING CONDITION OF SSD BASED ON CYCLE INFORMATION
App. No. 61/362,272
→
DATA DEPENDENT NOISE CALCULATION UNIT FOR FLASH CHANNEL
App. No. 61/361,891
→
OPTIMAL PROGRAM VERIFY AND READ LEVEL PLACEMENT TO REDUCE BER FOR AN SSD
App. No. 61/361,288
→
APPARATUS FOR STACKING INTEGRATED CIRCUITS
App. No. 12/828,175
→
SOLID-STATE DEVICE ENDURANCE
App. No. 61/349,701
→
FLASH STORAGE DEVICE WITH READ DISTURB MITIGATION
App. No. 12/779,001
→
FLASH STORAGE DEVICE WITH READ CACHE
App. No. 12/779,003
→
PARALLEL DATA STORAGE SYSTEM
App. No. 12/574,235
→
FLASH MEMORY ALLOCATION FOR IMPROVED PERFORMANCE AND ENDURANCE
App. No. 12/542,626
→
SYSTEM AND METHOD OF WEAR-LEVELING IN FLASH STORAGE
App. No. 12/511,994
→
FLASH STORAGE DEVICE WITH FLEXIBLE DATA FORMAT
App. No. 12/511,991
→
SYSTEM AND METHOD OF MAINTAINING DATA INTEGRITY IN A FLASH STORAGE DEVICE
App. No. 12/511,990
→
SYSTEM AND METHOD OF RECOVERING DATA IN A FLASH STORAGE SYSTEM
App. No. 12/511,989
→
FLASH STORAGE WITH INCREASED THROUGHPUT
App. No. 12/509,405
→
Storage Controller For Communicating With A Flash Storage System Including An Array Of Attached Of Attached Devices
App. No. 12/509,404
→
REMOVABLE POWER BACKUP FOR SSD
App. No. 61/228,132
→
COMPRESSION AND DECOMPRESSION IN SOLID-STATE STORAGE
App. No. 61/228,130
→
SYSTEM AND METHOD FOR PERFORMING A DIRECT MEMORY ACCESS AT A PREDETERMINED ADDRESS IN A FLASH STORAGE
App. No. 12/508,531
→
FLASH STORAGE SYSTEM AND METHOD FOR ACCESSING A BOOT PROGRAM
App. No. 12/508,528
→
READ/WRITE (IOPS) WITH EMBEDDED DRAM
App. No. 61/228,134
→
INTERLEAVED FLASH STORAGE SYSTEM AND METHOD
App. No. 12/508,538
→
ENHANCED MLC SOLID STATE DEVICE
App. No. 12/492,112
→
SOLID STATE DEVICE WITH ALLOCATED FLASH CACHE
App. No. 12/492,110
→
TABLE JOURNALING IN FLASH STORAGE DEVICES
App. No. 12/492,104
→
SLC-MLC COMBINATION FLASH STORAGE DEVICE
App. No. 12/492,113
→