IP Library › Assignment 036132/0780
Patent Assignment
Reel/Frame 036132/0780

Assignment of Assignor's Interest

Recorded: 2015-07-20 Pages: 3
Assignor
FUJITSU SEMICONDUCTOR LIMITED
Executed: 2015-05-02
Assignee
SOCIONEXT INC.
2-10-23, SHIN-YOKOHAMA, KOHOKU-KU, YOKOHAMA-SHI, KANAGAWA, 222-0033, JAPAN
Covered Properties (3)
Layout Verification Method and Verification Apparatus
Patent: 9,436,795 →
Application: 14/619,494 →
Publication: US 2015/0254392
Secure Processor System Without Need for Manufacturer and User to Know Encryption Information of Each Other
Application: 14/621,545 →
Publication: US 2015/0186679
Design Method and Design Apparatus
Patent: 9,659,119 →
Application: 14/629,910 →
Publication: US 2015/0278415
Related Assignments (3)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest Feb 12, 2015
From: ONODERA, MITSURU
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 034949/0017 →
Assignment of Assignor's Interest Feb 25, 2015
From: YAMAMOTO, FURUNA
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 035029/0643 →
Assignment of Assignor's Interest Nov 19, 2015
From: GOTO, SEIJI; KOYAMA, HIDENORI; KAMADA, JUN; MUKAI, SHINYA
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 037089/0217 →