Patent Assignment
Reel/Frame 042108/0880
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded: 2017-03-29
Received: 2017-03-29
Pages: 13
Assignor
CYPRESS SEMICONDUCTOR CORPORATION
Executed: 2017-03-22
Assignee
MONTEREY RESEARCH, LLC
3945 FREEDOM CIRCLE, SUITE 900, SANTA CLARA, CA, 95054, UNITED STATES
Covered Applications
(92)
RAPID MEMORY BUFFER WRITE STORAGE SYSTEM AND METHOD
App. No. 15/098,156
→
SIMULTANEOUS FORMATION OF A TOP OXIDE LAYER IN A SILICON-OXIDE-NITRIDE-OXIDE-SILICON (SONOS) TRANSISTOR AND A GATE OXIDE IN A METAL OXIDE SEMICONDUCTOR (MOS)
App. No. 14/599,157
→
AUTONOMOUS VEHICLE SEAT
App. No. 29/491,868
→
RAPID MEMORY BUFFER WRITE STORAGE SYSTEM AND METHOD
App. No. 13/764,602
→
SIMULTANEOUS FORMATION OF A TOP OXIDE LAYER IN A SILICON-OXIDE-NITRIDE-OXIDE-SILICON (SONOS) TRANSISTOR AND A GATE OXIDE IN A METAL OXIDE SEMICONDUCTOR (MOS)
App. No. 13/551,407
→
SIMULTANEOUS FORMATION OF A TOP OXIDE LAYER IN A SILICON-OXIDE-NITRIDE-OXIDE-SILICON (SONOS) TRANSISTOR AND A GATE OXIDE IN A METAL OXIDE SEMICONDUCTOR (MOS)
App. No. 12/782,699
→
DIGITAL FEEDBACK TECHNIQUE FOR REGULATORS
App. No. 12/621,311
→
RAPID MEMORY BUFFER WRITE STORAGE SYSTEM AND METHOD
App. No. 12/337,963
→
SPI ADDRESSING BEYOND 24-BITS
App. No. 12/277,911
→
Digital Feedback Technique for Regulators
App. No. 61/115,540
→
REPLICA TRANSISTOR VOLTAGE REGULATOR
App. No. 12/154,169
→
PROGRAMMABLE FLOATING GATE REFERENCE
App. No. 12/104,678
→
CHARGE PUMP TO SUPPLY VOLTAGE BANDS
App. No. 12/012,389
→
OPERATIONAL AMPLIFIER, LINE DRIVER, AND LIQUID CRYSTAL DISPLAY DEVICE
App. No. 12/000,995
→
VOLTAGE REGULATOR AND METHOD HAVING REDUCED WAKEUP-TIME AND INCREASED POWER EFFICIENCY
App. No. 11/999,676
→
SHORTED INPUT DETECTION FOR AMPLIFIER CIRCUITS
App. No. 11/818,172
→
Replica transistor voltage regulator architecture
App. No. 60/931,216
→
METHOD OF FABRICATING SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR MEMORY DEVICE DRIVER
App. No. 11/783,468
→
VOLTAGE STRESS TESTING OF CORE BLOCKS AND REGULATOR TRANSISTORS
App. No. 11/705,986
→
PULL-UP CIRCUIT FOR AN INPUT BUFFER
App. No. 11/654,445
→
METHOD FOR ON CHIP SENSING OF SONOS VT WINDOW IN NON-VOLATILE STATIC RANDOM ACCESS MEMORY
App. No. 11/647,017
→
Simultaneous Formation of a Top Oxide Layer in a Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) Transistor and a Gate Oxide in a Metal Oxide Semiconductor (MOS)
App. No. 11/615,683
→
COMBINATION SRAM AND NVSRAM SEMICONDUCTOR MEMORY ARRAY
App. No. 11/644,789
→
Voltage regulator and method having improved wakeup-time and power efficiency
App. No. 60/873,803
→
OFFSET VOLTAGE CORRECTION FOR HIGH GAIN AMPLIFIER
App. No. 11/636,347
→
Shorted input detection for a transimpedance amplifier
App. No. 60/840,272
→
PROGRAMMABLE ELECTROSTATIC DISCHARGE (ESD) PROTECTION DEVICE
App. No. 11/422,926
→
OPERATIONAL AMPLIFIER, LINE DRIVER, AND LIQUID CRYSTAL DISPLAY DEVICE
App. No. 11/448,669
→
DC LINEAR REGULATOR SINGLE CONTROLLER WITH PLURAL LOADS
App. No. 11/447,009
→
AMPLIFIER CIRCUIT WITH BIAS STAGE FOR CONTROLLING A COMMON MODE OUTPUT VOLTAGE OF THE GAIN STAGE DURING DEVICE POWER-UP
App. No. 11/420,948
→
High voltage tolerant pull up on input buffer
App. No. 60/781,918
→
CONTROL CIRCUIT AND CONTROL METHOD FOR DC-DC CONVERTER
App. No. 11/369,003
→
Method of voltage stress testing of core blocks and regulator fets
App. No. 60/773,001
→
Method of controlling a high voltage switch with low voltage control signals
App. No. 60/773,000
→
DC-DC CONVERTER AND ITS CONTROL METHOD, AND SWITCHING REGULATOR AND ITS CONTROL METHOD
App. No. 11/350,720
→
STRESS LINER FOR INTEGRATED CIRCUITS
App. No. 11/350,160
→
SEMICONDUCTOR DEVICE AND METHOD FOR CONTROLLING OPERATION THEREOF
App. No. 11/316,800
→
REPLICA REGULATOR WITH CONTINUOUS OUTPUT CORRECTION
App. No. 11/313,342
→
NONVOLATILE MEMORY DEVICE, AND ITS MANUFACTURING METHOD
App. No. 11/291,048
→
Amplifier circuit with bias stage for controlling a common mode output voltage of the gain stage during device power-up
App. No. 60/688,289
→
OPERATIONAL AMPLIFIER
App. No. 11/108,815
→
SHUNT TYPE VOLTAGE REGULATOR
App. No. 11/095,909
→
VOLTAGE REGULATOR CIRCUIT
App. No. 11/068,419
→
Replica regulator with continuous output correction
App. No. 60/639,009
→
REPLICA BIAS REGULATOR WITH SENSE-SWITCHED LOAD REGULATION CONTROL
App. No. 11/004,564
→
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
App. No. 10/986,652
→
REPLICA BIASED VOLTAGE REGULATOR
App. No. 10/965,445
→
SWITCHING REGULATOR CONTROL CIRCUIT, SWITCHING REGULATOR AND SWITCHING REGULATOR CONTROL METHOD
App. No. 10/948,644
→
Method of fabricating semiconductor memory device and semiconductor memory device driver
App. No. 10/916,410
→
METHOD FOR PULSE ERASE IN DUAL BIT MEMORY DEVICES
App. No. 10/899,684
→
RAMP SOURCE HOT-HOLE PROGRAMMING FOR TRAP BASED NON-VOLATILE MEMORY DEVICES
App. No. 10/863,933
→
OPERATIONAL AMPLIFIER, LINE DRIVER, AND LIQUID CRYSTAL DISPLAY DEVICE
App. No. 10/811,431
→
SIGNAL TRANSMISSION AMPLIFIER CIRCUIT
App. No. 10/797,147
→
Voltage regulator architecture and method of operating the same
App. No. 60/549,698
→
Replica biased voltage regulator
App. No. 60/531,911
→
PROCESS FOR FABRICATION OF SPACER LAYER WITH REDUCED HYDROGEN CONTENT IN SEMICONDUCTOR DEVICE
App. No. 10/731,494
→
Replica bias regulator with sense-switched load regulation control
App. No. 60/527,150
→
CIRCUIT AND TECHNIQUE FOR ACCURATELY SENSING LOW VOLTAGE FLASH MEMORY DEVICES
App. No. 10/679,179
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PORTABLE DEVICE HAVING A CHARGING CIRCUIT AND SEMICONDUCTOR DEVICE FOR USE IN THE CHARGING CIRCUIT OF THE SAME
App. No. 10/665,406
→
A FLASH MEMORY CELL WITH DRAIN AND SOURCE FORMED BY DIFFUSION OF A DOPANT FROM A SILICIDE
App. No. 10/661,720
→
CAM (CONTENT ADDRESSABLE MEMORY) CELLS AS PART OF CORE ARRAY IN FLASH MEMORY DEVICE
App. No. 10/650,049
→
PROGRAMMING OF A FLASH MEMORY CELL
App. No. 10/617,971
→
METHOD FOR PREDICTING REMAINING CHARGE OF PORTABLE ELECTRONICS BATTERY
App. No. 10/412,427
→
Single ended self-referencing amplifier for fast signal transfer
App. No. 60/457,751
→
DUAL TRISTATE PATH OUTPUT BUFFER CONTROL
App. No. 10/353,375
→
MEMORY CIRCUIT ARRANGEMENT FOR PROGRAMMING A MEMORY CELL
App. No. 10/348,732
→
METHOD FOR PRODUCING A LOW DEFECT HOMOGENEOUS OXYNITRIDE
App. No. 10/306,382
→
METHOD OF PROGRAMMING IN-SERIES MEMORY CELLS
App. No. 10/282,847
→
METHOD OF FABRICATING SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR MEMORY DEVICE DRIVER
App. No. 10/279,981
→
A MULTI-BIT SILICON NITRIDE CHARGE-TRAPPING NON-VOLATILE MEMORY CELL
App. No. 10/247,641
→
VIRTUAL GROUND SILICIDE BIT LINE PROCESS FOR FLOATING GATE FLASH MEMORY
App. No. 10/238,412
→
METHOD FOR REPAIRING OVER-ERASURE OF FAST BITS IN FLOATING GATE MEMORY DEVICES
App. No. 10/215,140
→
2BIT/CELL ARCHITECTURE FOR FLOATING GATE FLASH MEMORY PRODUCT AND ASSOCIATED METHOD
App. No. 10/180,673
→
REPLACING LAYERS OF AN INTERGATE DIELECTRIC LAYER WITH HIGH-K MATERIAL FOR IMPROVED SCALABILITY
App. No. 10/145,952
→
OPERATIONAL AMPLIFIER
App. No. 10/108,341
→
REGULATOR CIRCUIT AND CONTROL METHOD THEREOF
App. No. 10/101,976
→
FLASH MEMORY ARRAY ARCHITECTURE HAVING STAGGERED METAL LINES
App. No. 10/096,313
→
METHOD AND APPARATUS FOR PRE-CHARGING NEGATIVE PUMP MOS REGULATION CAPACITORS
App. No. 10/050,342
→
NONVOLATILE SEMICONDUCTOR MEMORY
App. No. 10/043,114
→
DUAL TRISTATE PATH OUTPUT BUFFER CONTROL
App. No. 09/997,130
→
METHOD OF FABRICATING DOUBLE DENSED CORE GATES IN SONOS FLASH MEMORY
App. No. 09/971,483
→
FLASH MEMORY DEVICE WITH INCREASE OF EFFICIENCY DURING AN APDE (AUTOMATIC PROGRAM DISTURB AFTER ERASE) PROCESS
App. No. 09/969,572
→
NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND FABRICATION PROCESS THEREOF
App. No. 09/963,632
→
Semiconductor device and method of manufacturing the same
App. No. 09/922,786
→
METHOD OF PROGRAMMING A NON-VOLATILE MEMORY CELL USING A VERTICAL ELECTRIC FIELD
App. No. 09/899,721
→
LOW COLUMN LEAKAGE NOR FLASH ARRAY-DOUBLE CELL IMPLEMENTATION
App. No. 09/884,565
→
Flash memory device with increase of efficiency during an APDE (authomatic program disturb after erase) process
App. No. 60/291,861
→
METHOD OF CHANNEL HOT ELECTRON PROGRAMMING FOR SHORT CHANNEL NOR FLASH ARRAYS
App. No. 09/861,031
→
SEMICONDUCTOR MEMORY DEVICE HAVING SOURCE AREAS OF MEMORY CELLS SUPPLIED WITH A COMMON VOLTAGE
App. No. 09/818,652
→
CHARGE CIRCUIT THAT PERFORMS CHARGE CONTROL BY COMPARING A PLURALITY OF BATTERY VOLTAGES
App. No. 09/815,049
→
PROCESS FOR MAKING A DUAL BIT MEMORY DEVICE WITH ISOLATED POLYSILICON FLOATING GATES
App. No. 09/810,155
→
DC-DC converter and semiconductor integrated circuit device for DC-DC converter
App. No. 09/769,240
→