Patent Assignment
Reel/Frame 045782/0028
RELEASE OF SECURITY INTEREST
Recorded: 2018-03-29
Received: 2018-03-29
Pages: 7
Assignor
MORGAN STANLEY SENIOR FUNDING, INC.
Executed: 2018-03-23
Assignee
CYPRESS SEMICONDUCTOR CORPORATION
198 CHAMPION COURT, SAN JOSE, CA, 95134, UNITED STATES
Covered Applications
(24)
HIGH VOLTAGE SWITCH PRE-DRIVER CIRCUIT
App. No. 12/690,067
→
DELAY CIRCUIT LIMIT DETECTION CIRCUIT AND METHOD
App. No. 11/699,951
→
SWITCH PRE-DRIVER SYSTEM AND METHOD
App. No. 11/588,543
→
POINT AND CLICK EXPRESSION BUILDER
App. No. 11/512,545
→
AGILE, LOW PHASE NOISE CLOCK SYNTHESIZER AND JITTER ATTENUATOR
App. No. 11/425,634
→
MEMORY DEVICE AND METHOD FOR FAST CROSS ROW DATA ACCESS
App. No. 11/391,535
→
Frequency limit detection circuit
App. No. 60/763,508
→
LOW POWER BANDGAP REFERENCE CIRCUIT WITH INCREASED ACCURACY AND REDUCED AREA CONSUMPTION
App. No. 11/321,854
→
Point and click expression builder
App. No. 60/741,948
→
High-voltage switch pre-driver circuit
App. No. 60/731,102
→
Agile, low phase noise clock synthesizer and jitter attenuator
App. No. 60/693,023
→
Memory device and method for no latency cross row data access
App. No. 60/667,149
→
CIRCUIT AND METHOD FOR MONITORING THE STATUS OF A CLOCK SIGNAL
App. No. 11/097,527
→
METHOD TO ELIMINATE INVERSE NARROW WIDTH EFFECT IN SMALL GEOMETRY MOS TRANSISTORS
App. No. 10/739,674
→
USE OF HIGH-K DIELECTRIC MATERIAL IN MODIFIED ONO STRUCTURE FOR SEMICONDUCTOR DEVICES
App. No. 10/646,080
→
ALUMINUM-FILLED VIA STRUCTURE WITH BARRIER LAYER
App. No. 10/308,410
→
METHOD OF MANUFACTURING A DIELECTRIC LAYER FOR A SILICON-OXIDE-NITRIDE-OXIDE-SILICON (SONOS) TYPE DEVICES
App. No. 10/185,470
→
METHOD OF MANUFACTURING AN OXIDE-NITRIDE-OXIDE (ONO) DIELECTIC FOR SONOS-TYPE DEVICES
App. No. 10/184,715
→
USE OF HIGH-K DIELECTRIC MATERIALS IN MODIFIED ONO STRUCTURE FOR SEMICONDUCTOR DEVICES
App. No. 10/036,757
→
METHOD OF MANUFACTURING A TOP INSULATING LAYER FOR A SONOS-TYPE DEVICE
App. No. 10/054,515
→
SALICIDED GATE FOR VIRTUAL GROUND ARRAYS
App. No. 09/968,465
→
METHOD TO ELIMINATE INVERSE NARROW WIDTH EFFECT IN SMALL GEOMETRY MOS TRANSISTORS
App. No. 09/929,829
→
SEMICONDUCTOR DEVICE HAVING SILICON-RICH LAYER AND METHOD OF MANUFACTURING SUCH A DEVICE
App. No. 09/920,378
→
MICROCONTROLLER INPUT/OUTPUT NODES WITH BOTH PROGRAMMABLE PULL-UP AND PULL-DOWN RESISTIVE LOADS AND PROGRAMMABLE DRIVE STRENGTH
App. No. 09/909,527
→