Assignment of Assignor's Interest

Recorded: 2018-09-10 Pages: 3

Assignors

LAWSON, RANDALL SCOTT

Executed: 2018-09-06

BHATTACHARYYA, UTPAL

Executed: 2018-09-07

ACHESON, EDWARD B.

Executed: 2018-09-07

ROESLER, ROBERT

Executed: 2018-09-09

Assignee

CADENCE DESIGN SYSTEMS, INC.

2655 SEELY AVENUE, SAN JOSE, CALIFORNIA, 95134

Covered Property (1)

Process for Analyzing Printed Circuit Board and Packaging Manufacturing Design Rules

Patent: 10,691,868 →

Application: 16/126,734 →