Patent Assignment
Reel/Frame 047066/0249
Assignment of Assignor's Interest
Recorded: 2018-10-04
Pages: 8
Assignors
BIBIKAR, VASUDEV
Executed: 2017-10-02
RAMACHANDRAN, ASWIN
Executed: 2017-10-02
LU, CHIN SENG
Executed: 2017-10-04
RAJESH, MOORTHY
Executed: 2018-08-16
CREWS, DARREN S.
Executed: 2018-08-21
Assignee
INTEL CORPORATION
2200 MISSION COLLEGE BOULEVARD, SANTA CLARA, CALIFORNIA, 95054
Covered Property
(1)
Mechanism to Enter or Exit Retention Level Voltage While a System-on-a-Chip Is in Low Power Mode